ATSAM2133B ATMEL Corporation, ATSAM2133B Datasheet - Page 8

• Manufacturer Part Number: ATSAM2133B
• Description: Low-power Synthesizer
• Manufacturer: ATMEL Corporation

100-ball LFBGA Package
Table 3. Pin by Function - 100-ball LFBGA Package
8
Pin Name
GND
VC2
VC3
PWRIN
PWROUT
D0 - D7
CS
WR
RD
A0
IRQ
RESET
X1, X2
CKOUT
DABD0 - 1
CLBD
WSBD
DAAD
P0 - P3
DBCLK
DBDATA
DBACK
MIDI IN
MIDI OUT
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ATSAM2133B
Pin Number
A3, A9, C7, D5,
D10, E1, F7, G4,
G5, J5, J8
B6, C5, C6, E2, H6
C3, D8, G2, G10,
H4, H7
A8
B7
E4, D1, E3, F4, F3,
F5, F2, F1
C1
C2
D2
D3
B1
H3
D6, A7
E5
A4, B4
C4
B3
A2
G1, G3, H2, H1
A5
D4
B5
A1
B2
TSOUT
Type
PWR
PWR
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
I/O
I/O
I/O
IN
IN
IN
IN
IN
IN
IN
IN
-
switch is used for minimum power-down consumption, then all these pins should be
connected to PWROUT, the output of the built-in power switch.
should be lower than V
pin must be connected to nominal 2.5V
pins.
8-bit data bus to host processor. Information on these pins is parallel MIDI (MPU-401
type applications).
Read from host, active low.
0: data registers (read/write)
1: status register (read) control register (write)
frequency is internally multiplied by 4 to provide the IC master clock. An external
11.2896 MHz clock can also be used on X1 (2.5V
cannot be used to drive external ICs; use CKOUT instead.
Buffered X2 output. Can be used to drive external DAC master clock (256 * Fs)
(2 x 32) of serial data per frame. Audio data precise up to 20 bits. DABD0 can hold
additional control data (mute, A/D gain, D/A gain, etc.)
Audio data bit clock, provides timing to DABD0 - 1, DAAD.
Audio data word select. The timing of WSBD can be selected to be I2S or Japanese
compatible.
Debug clock. Should be connected to V
low just after RESET, then the internal ROM debugger/flash programmer is started
Debug data. Allows serial communication for debug/flash programming
Debug ack. Toggled each time a bit is received/sent on DBDATA
Power ground - all GND pins should be returned to digital ground
Core power +2.5V ±10%. All V
Periphery power 2.25V to 3.7V. All V
Power switch input, 2.25V to 2.95V. Even if the power switch feature is not used, this
Power switch output. Use this pin to supply 2.5V core power by connecting it to all V
Chip select from host, active low.
Write from host, active low.
Selects MPU-401 internal registers:
Tri-state output pin, active high.
Master reset input, active low.
Crystal connection. Crystal frequency should be Fs * 256 (typ 11.2896 MHz). Crystal
Two stereo serial audio data output (4 audio channels). Each output holds 64 bits
Stereo serial audio data input.
General-purpose programmable I/O pins.
MIDI IN input
MIDI OUT output
Function
C2
.
C2
pins should be returned to +2.5V. If the built-in power
C3
pins should be returned to nominal +3.3V. V
C3
under normal operation. If DBCLK is found
PP
max through 47 pF capacitor). X2
2694A–DRMSD–05/03
C3
C2