IDT70V05 Integrated Device Technology, IDT70V05 Datasheet - Page 9

• Manufacturer Part Number: IDT70V05
• Description: High-speed 3.3v 8k X 8 Dual-port Static Ram
• Manufacturer: Integrated Device Technology

Waveform of Read Cycles
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
3. t
4. Start of valid data depends on which timing becomes effective last t
5. SEM = V
IDT70V05S/L
High-Speed 3.3V 8K x 8 Dual-Port Static RAM
DATA
BUSY
relation to valid output data.
BDD
ADDR
delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no
R/W
OUT
OUT
OE
CE
IH
.
t
t
t
t
ACE
AOE
AA
LZ
(4)
(1)
(5)
(4)
(4)
AOE
, t
ACE
t
RC
, t
AA
6.42
t
or t
BDD
9
BDD
VALID DATA
(3,4)
.
(4)
Industrial and Commercial Temperature Ranges
t
HZ
t
OH
(2)
2941 drw 07