IDT82V3012 Integrated Device Technology, IDT82V3012 Datasheet - Page 16

• Manufacturer Part Number: IDT82V3012
• Description: T1/e1/oc3 Wan Pll With Dual Reference Inputs
• Manufacturer: Integrated Device Technology

2.11
required to minimize supply noise modulation of the output clocks. The
common sources of power supply noise are switching power supplies
and the high switching noise from the outputs to the internal PLL. The
82V3012 provides separate power pins: V
for the internal analog PLL, and V
as I/O driver circuits.
Functional Description
IDT82V3012
To achieve optimum jitter performance, power supply filtering is
IDT82V3012
POWER SUPPLY FILTERING TECHNIQUES
Figure - 9 Power-Up Reset Circuit
3.3 V
3.3 V
SLF7028T-100M1R1
SLF7028T-100M1R1
RST
DDD
pins are for the core logic as well
1 kΩ
Rp
DDA
10 µF
10 µF
and V
Figure - 10 IDT82V3012 Power Decoupling Scheme
10 kΩ
R
DDD
3.3 V
. V
1 µF
C
DDA
pins are
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
16
48
19
26
37
13
switching regulator, the power supply output should be filtered with
sufficient bulk capacity to minimize ripple and 0.1 uF (0402 case size,
ceramic) capacitors to filter out the switching transients.
individually. V
power supply plane through vias, and bypass capacitors should be used
for each pin.
bead should be connected to each power pin.
can be achieved by using one 10 uF (1210 case size, ceramic) and at
least two 0.1 uF (0402 case size, ceramic) capacitors in parallel. The 0.1
uF (0402 case size, ceramic) capacitors must be placed next to the
V
be of 1210 case size, and it must be ceramic for lowest possible ESR
(Effective Series Resistance). The 0.1 uF should be of case size 0402,
which offers the lowest ESL (Effective Series Inductance) to achieve low
impedance towards the high speed range.
uF (1210 case size, ceramic) capacitors are recommended. The 0.1 uF
capacitors should be placed as close to the V
V
V
V
V
V
DDA
DDA
DDA
DDD
DDD
DDD
To minimize switching power supply noise generated by the
For the 82V3012, the decoupling for V
The analog power supply V
For V
Please refer to evaluation board schematic for details.
T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
pins and as close as possible. Note that the 10 uF capacitor must
IDT82V3012
DDD
, at least three 0.1 uF (0402 case size, ceramic) and one 10
DDD
Figure - 10
and V
V
V
V
V
V
DDA
SS
SS
SS
SS
SS
illustrates how bypass capacitor and ferrite
12
18
27
38
47
should be individually connected to the
DDA
should have low impedance. This
DDA
DDD
and V
pins as possible.
DDD
May 24, 2006
are handled