IDT82V3012 Integrated Device Technology, IDT82V3012 Datasheet - Page 8

• Manufacturer Part Number: IDT82V3012
• Description: T1/e1/oc3 Wan Pll With Dual Reference Inputs
• Manufacturer: Integrated Device Technology

Pin Description
IDT82V3012
C19POS
C19NEG
C2/C1.5
Name
C1.5o
TRST
C19o
C32o
C16o
F19o
F32o
F16o
TDO
TMS
RSP
TSP
TCK
C8o
C4o
C2o
C3o
C6o
F8o
F0o
TDI
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(LVDS) O
Type
I
I
I
I
Pin Number
21
22
43
25
24
23
20
17
16
15
14
54
49
40
39
36
33
41
42
29
32
30
28
31
19.44 MHz Clock Output (LVDS Level).
This pair of outputs is used for OC3/STS3 applications.
19.44 MHz Clock Output (CMOS Level).
This output is used for OC3/STS3 applications.
32.768 MHz Clock Output.
This output is a 32.768 MHz clock used for ST-BUS operation.
16.384 MHz Clock Output.
This output is a 16.384 MHz clock used for ST-BUS operation.
8.192 MHz Clock Output.
This output is an 8.192 MHz clock used for ST-BUS operation.
4.096 MHz Clock Output.
This output is a 4.096 MHz clock used for ST-BUS operation.
2.048 MHz Clock Output.
This output is a 2.048 MHz clock used for ST-BUS operation.
3.088 MHz Clock Output.
This output is used for T1 applications.
1.544 MHz Clock Output.
This output is used for T1 applications.
6.312 MHz Clock Output.
This output is used for DS2 applications.
2.048 MHz or 1.544 MHz Clock Output.
This output is a 2.048 MHz or 1.544 MHz clock signal. If the selected reference input (Fref0 or Fref1) is 8 kHz, 2.048
MHz, or 19.44 MHz, the C2/C1.5 pin will output a 2.048 MHz clock signal. If the frequency of the selected reference
input (Fref0 or Fref1) is 1.544 MHz, the C2/C1.5 pin will output a 1.544 MHz clock signal. Refer to
details.
8 kHz Frame Signal with 19.44 MHz Pulse Width.
This output is used for OC3/STS3 applications.
Frame Pulse ST-BUS 8.192 Mb/s.
This is an 8 kHz 30 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This framing signal
is typically used for ST-BUS operation at 8.192 Mb/s.
Frame Pulse ST-BUS 8.192 Mb/s.
This is an 8 kHz 61 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This framing signal
is typically used for ST-BUS operation at 8.192 Mb/s.
Frame Pulse.
This is an 8 kHz 122 ns active high framing pulse, which marks the beginning of a frame.
Frame Pulse ST-BUS 2.048 Mb/s.
This is an 8 kHz 244 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This framing
signal is typically used for ST-BUS operation at 2.048 Mb/s and 4.096 Mb/s.
Receive Sync Pulse.
This is an 8 kHz 488 ns active high framing pulse, which marks the beginning of a ST-BUS frame. This framing
signal is typically used to connect to the Siemens MUNICH-32 device.
Transmit Sync Pulse.
This is an 8 kHz 488 ns active high framing pulse, which marks the beginning of an ST-BUS frame. This framing is
typically used to connect to the Siemens MUNICH-32 device.
Test Serial Data Out.
JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when
JTAG scan is not enabled.
Test Serial Data In.
JTAG serial test instructions and data are shifted in on this pin. This pin is internally pulled up to V
Test Reset.
Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin is internally
pulled up to V
Test Clock.
Provides the clock for the JTAG test logic.
Test Mode Select.
JTAG signal that controls the state transitions of the TAP controller. This pin is internally pulled up to V
DDD
. It is connected to the ground for normal applications.
8
T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
Description
DDD
Table - 5
May 24, 2006
.
DDD
.
for