IDT82V3012 Integrated Device Technology, IDT82V3012 Datasheet - Page 2

• Manufacturer Part Number: IDT82V3012
• Description: T1/e1/oc3 Wan Pll With Dual Reference Inputs
• Manufacturer: Integrated Device Technology

DESCRIPTION
inputs. It contains a Digital Phase-Locked Loop (DPLL), which
generates low jitter ST-BUS and 19.44 MHz clock and framing signals
that are phase locked to an 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz
input reference.
C2o, C4o, C8o, C16o, C19o, C32o) and 7 types of framing signals (F0o,
F8o, F16o, F19o, F32o, RSP, TSP) for multitrunk T1/E1 and STS3/OC3
links.
PIN CONFIGURATION
Description
IDT82V3012
The IDT82V3012 is a T1/E1/OC3 WAN PLL with dual reference
The IDT82V3012 provides 9 types of clock signals (C1.5o, C3o, C6o,
The IDT82V3012 is compliant with AT&T TR62411, Telcordia GR-
MODE_sel0
MODE_sel1
MON_out0
MON_out1
C19NEG
C19POS
F0_sel1
F0_sel0
IN_sel
TCLR
C1.5o
Figure - 1 IDT82V3012 SSOP56 Package Pin Assignment
Fref0
Fref1
C16o
C32o
V
V
V
RST
TCK
C6o
C3o
C2o
C4o
C8o
V
V
DDD
V
DDD
DDD
SS
SS
SS
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
IDT82V3012
2
1244-CORE Stratum 3, Stratum 4 Enhanced and Stratum 4, ETSI ETS
300 011, ITU-T G.813 Option 1, and ITU-T G.812 Type IV clocks. It
meets the jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/
wander, frequency accuracy, capture range, phase change slope,
holdover frequency accuracy and MTIE (Maximum Time Interval Error)
requirements for these specifications.
for T1, E1 and OC3 systems, or used as ST-BUS clock and frame pulse
source. It also can be used in access switch, access routers, ATM edge
switches, wireless base station controllers, or IADs (Integrated Access
Devices), PBXs, line cards and SONET/SDH equipments.
The IDT82V3012 can be used in synchronization and timing control
T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS
56
54
37
36
35
34
32
31
55
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
33
30
29
TIE_en
IC0
HOLDOVER
FREERUN
OSCi
F19o
V
V
NORMAL
FLOCK
LOCK
C19o
TSP
RSP
F32o
F16o
V
F8o
F1_sel0
F1_sel1
F0o
TDI
TMS
TRST
TDO
IC2
C2/C1.5
V
DDA
SS
DDA
SS
May 24, 2006