MCP1726T-ADJZEMF Microchip Technology, MCP1726T-ADJZEMF Datasheet - Page 30

• Manufacturer Part Number: MCP1726T-ADJZEMF
• Description: Regulator, Extended Industrial, HVSON, 8-Pin|
• Manufacturer: Microchip Technology

PIC12F683
3.6.8
When switching from the secondary back to the
primary system clock by clearing the SCS bit
(OSCCON<0>), the sequence of events that take place
will depend upon the value of the F
configuration word. If the primary clock source is
configured as a crystal (HS, XT, or LP), then the
transition will take place after 1024 clock cycles. This
allows time for the crystal oscillator to power-up and
stabilize prior to the switchover.
During the oscillator start-up time, the system clock
comes from the secondary clock source, INTOSC. The
OSTS bit (OSCCON<3>) can be monitored to indicate
when the switchover is complete.
Following the oscillator start-up time, the internal Q
clocks are held in the Q1 state until next falling edge
clock of the primary system clock. The clock input to
the Q clocks is then released, and operation resumes
with primary system clock determined by the F
(see Figure 3-8).
FIGURE 3-8:
DS41211A-page 28
Note:
SYSTEM CLOCK
PROGRAM
COUNTER
INTOSC
SECONDARY TO PRIMARY
OSCILLATOR SWITCH
If the primary system clock is either RC or
EC, an internal delay timer (5-10 s) will
suspend operation after exiting Secondary
Oscillator mode to allow the CPU to
stabilize prior to code execution.
OSC1
OSC2
Note 1: T
SCS
2: T
3: T
Q1
SECONDARY TO PRIMARY OSCILLATOR (XT, LP OR HS) SWITCH
T
T
OSC
SCS
INT
0
INT
= 32 s maximum.
= 1 T
= 50 ns minimum.
Q2
1
INT
T
T
OST
.
Q3
1022 1023
OSC
PC
bits in the
Q4
Advance Information
OSC
bits
Q1
T T
SCS
Q2
3.6.8.1
Changing from secondary to primary clock source can
be accomplished by clearing the SCS bit.
This is the sequence of events that follows:
1.
2.
3.
4.
5.
6.
If the primary system clock is configured as EC
or RC, then the OST time-out is skipped. Skip to
step 3.
If the primary system clock is configured as an
external oscillator (HS, XT, LP), then the OST
will be active, waiting for 1024 clocks of the
primary system clock. The device will use the
INTOSC as the system clock during this time.
On the following Q1, the device holds the
system clock in Q1.
The device stays in Q1 until the next falling edge
of the primary system clock.
Once the switch over is complete, the device
begins to run from the primary oscillator.
If the INTOSC or INTRC is not required, the
unused oscillator will be shut down to save
current. The INTRC will not be disabled if it is
being used for any other function, such as WDT,
or Fail-Safe Clock Monitoring.
T
T
OSC
PC + 1
Returning to Primary Oscillator
Source Sequence
Q3
 2003 Microchip Technology Inc.
Q4
PC + 2
Q1