MCP1726T-ADJZEMF Microchip Technology, MCP1726T-ADJZEMF Datasheet - Page 85

• Manufacturer Part Number: MCP1726T-ADJZEMF
• Description: Regulator, Extended Industrial, HVSON, 8-Pin|
• Manufacturer: Microchip Technology

12.3.7
On power-up, the time-out sequence is as follows:
first, PWRT time-out is invoked after POR has expired.
Then, OST is activated. The total time-out will vary
based on oscillator configuration and PWRTE bit
status. For example, in EC mode with PWRTE bit
erased (PWRT disabled), there will be no time-out at
all. Figure 12-4, Figure 12-5 and Figure 12-6 depict
time-out sequences. The device can execute code
from the INTOSC while OST is active by enabling
Two-speed
Section 12.6.3.1 “Two-speed Start-up Sequence”
and Section 12.6.4.1 “Fail-Safe Mode”).
Since the time-outs occur from the POR pulse, if
MCLR is kept low long enough, the time-outs will
expire. Then bringing MCLR high will begin execution
immediately (see Figure 12-5). This is useful for
testing purposes or to synchronize more than one
PIC12F683 device operating in parallel.
Table 12-6 shows the Reset conditions for some
special registers, while Table 12-4 shows the Reset
conditions for all the registers.
TABLE 12-1:
TABLE 12-2:
TABLE 12-3:
 2003 Microchip Technology Inc.
03h
8Eh
Legend:
Note 1:
Address Name
Legend: u = unchanged, x = unknown
Oscillator Configuration
POR
0
1
u
u
u
u
RC, EC, INTOSC
XT, HS, LP
STATUS
PCON
u = unchanged, x = unknown, — = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are
not used by BOD.
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
TIME-OUT SEQUENCE
Start-up
BOD
u
0
u
u
u
u
TIME-OUT IN VARIOUS SITUATIONS
STATUS/PCON BITS AND THEIR SIGNIFICANCE
SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT
Bit 7
IRP
—
or
TO
1
1
0
0
u
1
Fail-Safe
Bit 6
RP1
—
PWRTE = 0
1024•T
T
T
PWRT
PD
PWRT
ULPWUE SBODEN
1
1
u
0
u
0
Bit 5
RPO
Monitor
OSC
+
Power-up
Advance Information
Power-on Reset
Brown-out Detect
WDT Reset
WDT Wake-up
MCLR Reset during normal operation
MCLR Reset during Sleep
Bit 4
TO
(see
PWRTE = 1
1024•T
—
Bit 3
OSC
PD
—
12.3.8
The Power Control/Status Register, PCON (address
8Eh) has two status bits to indicate what type of Reset
that last occurred.
Bit0 is BOD (Brown-out). BOD is unknown on Power-
on Reset. It must then be set by the user and checked
on subsequent Resets to see if BOD = 0, indicating
that a brown-out has occurred. The BOD Status bit is a
don’t care and is not necessarily predictable if the
brown-out circuit is disabled (BODEN<1:0> = 00 in
the configuration word).
Bit1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a
subsequent Reset, if POR is ‘0’, it will indicate that a
Power-on Reset has occurred (i.e., V
gone too low).
For more information, see Section 4.2.3 “Ultra Low-
power Wake-up” and Section 12.3.5 “Brown-Out
Detect (BOD)”.
Bit 2
—
PWRTE = 0
Z
1024•T
T
T
PWRT
PWRT
Brown-out Detect
Bit 1
POWER CONTROL (PCON) STATUS
REGISTER
POR
OSC
DC
+
Bit 0
BOD
C
PWRTE = 1
1024•T
PIC12F683
—
POR, BOD
0001 1xxx
--01 --qq
Value on
OSC
DS41211A-page 83
DD
from Sleep
1024•T
Wake-up
Value on all
000q quuu
--0u --uu
Resets
may have
—
other
OSC
(1)