TDA9330 Philips Semiconductors, TDA9330 Datasheet - Page 14

• Manufacturer Part Number: TDA9330
• Description: I2C-bus controlled TV display processors
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Table 27 Long blanking mode
Table 28 Vertical free-running frequency in TV mode
Table 29 De-interlace phase
Table 30 Switch-off in vertical overscan
Table 31 Select vertical frequency
Table 32 Enable vertical guard (RGB blanking)
Table 33 Interlace
2000 May 08
LBM
OSO
EVG
I
SVF
VFF
DIP
DL
2
0
1
0
1
0
1
0
1
0
1
0
1
0
1
C-bus controlled TV display processors
delay of 1st field (start of synchronized V
pulse coincides with H-flyback) with 0.5 H
fixed in accordance with 50 Hz standard
50 Hz (SVF = 0) or 100 Hz (SVF = 1)
60 Hz (SVF = 0) or 120 Hz (SVF = 1)
vertical frequency is 100 or 120 Hz
adapted to standard (50 or 60 Hz)
vertical frequency is 50 or 60 Hz
switch-off in vertical overscan
delay of 2nd field with 0.5 H
VERTICAL GUARD MODE
switch-off undefined
BLANKING MODE
FREQUENCY
de-interlace
not active
STATUS
interlace
PHASE
MODE
MODE
active
D
14
Table 34 Soft clipping level
Table 35 Clamp pulse timing
Note
1. See Chapter “Characteristics”; note 13.
Table 36 Start line blanking (15 steps; 2 line locked clock
Note
1. See Chapter “Characteristics”; note 13.
Output status bits
Table 37 Power-on reset
Table 38 Field frequency indication
Table 39 Phase 1 (
HDCL
LBL3
POR
SC1
FSI
SL
0
0
1
1
0
1
0
0
1
0
1
0
1
0
1
period per step; 1 line period is 440 LLC pulses)
LBL2
SC0
0
1
0
1
0
1
1
1
BETWEEN SOFT CLIPPING AND
LBL1
) lock indication
0
1
1
VOLTAGE DIFFERENCE
FREQUENCY
normal timing
HDTV timing
50 or 100 Hz
60 or 120 Hz
INDICATION
power-down
not locked
TDA933xH series
MODE
10% above PWL
normal
MODE
locked
0% above PWL
5% above PWL
LBL0
soft clipping off
0
1
1
Preliminary specification
PWL
(1)
BLANKING
START LINE
+14 LLC
normal
16 LLC
(1)