TDA9330 Philips Semiconductors, TDA9330 Datasheet - Page 31

• Manufacturer Part Number: TDA9330
• Description: I2C-bus controlled TV display processors
• Manufacturer: Philips Semiconductors

Philips Semiconductors
19. The control circuit contains a PWL circuit and a soft clipper.
20. The above-mentioned output amplitude range at which the PWL detector is activated is valid for nominal settings of
21. The soft clipper gain reduction is measured by applying a sawtooth signal with rising slope and 1 V (b-w) at the
22. When the blue stretch function is activated (via I
23. Switch-off behaviour of TDA933xH. For applications with an EHT generator without bleeder resistor, the picture tube
24. The set is switched to standby via the I
25. The set is switched off via the mains power switch. When the mains supply is switched off, the supply voltage of the
2000 May 08
I
2
clamped and the maximum sink current is approximately 100 A. The voltage on the pin must not exceed the supply
voltage.
a) The detection level of the PWL can be adjusted via the I
b) In addition to the PWL circuit, the IC contains a soft clipper function which limits short transients that exceed the
the white point controls, and when the CCC loop is switched off or set to 1-point stabilization mode. In 2-point
stabilization mode, the mentioned range is only valid when the gain of the RGB output stages is dimensioned such
that the RGB output amplitudes are 2 V (b-w) for nominal contrast setting, see also note 11.
luminance input. To prevent the beam current limiter from operating, a DC voltage of 3.5 V must be applied to pin 43.
The contrast is set at the maximum value, the PWL at the minimum value, and the soft clipping level is set at 0%
above the PWL (SC
at the beginning and end of the sawtooth. The soft clipper gain reduction is defined as the ratio of the slopes of the
tangents for black and white, see Fig.9.
for input signals that exceed a value of 80% of the nominal amplitude. The result is that the white point is shifted to
a higher colour temperature.
capacitance can be discharged with a fixed beam current when the set is switched off. The magnitude of the
discharge current is controlled via the black current loop. The fixed beam current mode can be activated with bit FBC.
With the fixed beam current option activated, it is still possible to have a black screen during switch-off. This is
realized by placing the vertical deflection in the overscan position. This mode is activated by bit OSO. There are two
possible situations for switch-off (see notes 24 and 25).
a) Vertical scan is completed.
b) Vertical flyback is completed.
c) Slow stop of the horizontal output is started, by gradually reducing the ‘on-time’ at the horizontal output from
d) At the same moment, the fixed beam current is forced via the black current loop (if FBC = 1).
e) If OSO = 1, the vertical deflection stays in overscan position; if OSO = 0, the vertical deflection keeps running.
f) The slow stop time is approximately 50 ms, the fixed beam current flows for 18.6 ms or 25 ms, depending on the
line deflection circuit of the TV set will decrease. A detection circuit must be made that monitors this supply voltage.
C-bus controlled TV display processors
This amplitude is related to the Y input signal, typical amplitude 1 V (b-w), at maximum contrast setting. The
detector measures the amplitude of the RGB signals after the contrast control. The output signal of the PWL
detector is filtered by an external capacitor, so that short transients in the video signal do not activate the limiting
action. Because the capacitor is externally available at pin 34, the set maker can adapt the filter time constant as
required. The contrast reduction of the PWL is obtained by discharging the external capacitor at the beam current
limiting input (pin 43). To avoid the PWL circuit from reducing the contrast of the main picture when the amplitude
of the inserted RGB2 signal is too high, the output current of the PWL detector is disabled when the fast blanking
input (pin 38) is high. In blending mode (OBL = 1), the PWL detector is disabled when the blending voltage is
above the 50% insertion level. The soft clipper circuit will still limit the peak voltage at the RGB outputs.
PWL. The difference between the PWL and the soft clipping level can be adjusted between 0 and 10% in
three steps via the I
also possible to switch off the soft clipping function.
nominal to zero.
value of bit TFBC, see Fig.15.
10
= 00). The tangents of the sawtooth waveform at one of the RGB outputs is now determined
2
C-bus, with bus bits SC1 and SC0 (soft clipping level equal or higher than the PWL). It is
2
C-bus. In this situation, the procedure is as follows:
2
C-bus bit BLS), the gain of the red and green channels is reduced
31
2
C-bus in a control range between 0.65 and 1.0 V (b-w).
TDA933xH series
Preliminary specification