TDA9330 Philips Semiconductors, TDA9330 Datasheet - Page 33

• Manufacturer Part Number: TDA9330
• Description: I2C-bus controlled TV display processors
• Manufacturer: Philips Semiconductors

Philips Semiconductors
36. This parameter is not tested during production and is just given as application information for the designer of the
37. The rise and fall times of the blanking pulse and clamping pulse at the sandcastle output (pin 9) depend on the
38. The vertical guard pulse from the vertical output stage should fall within the vertical blanking period
39. Switching between the 1f
40. The vertical linearity is measured on the differential output current at the vertical drive output (pins 1 and 2) for zero
41. The field detection mechanism is explained in Fig.17.
42. Output range percentages mentioned for E-W control parameters are based on the assumption that the E-W
43. The IC has protection inputs for flash protection and overvoltage protection.
44. The ICs have a zoom adjustment possibility for the horizontal and vertical deflection. For this reason, an extra DAC
2000 May 08
I
2
a) For picture tubes with Dynamic Astigmatic Focusing (DAF) guns, the rise of the EHT voltage between
b) During switch-off, the slow-stop function is active. This is realized by decreasing the t
c) The horizontal output is gated with the flyback pulse so that the horizontal output transistor cannot be switched
television receiver.
capacitive load. The value of the source current during the rising edge or sink current during the falling edge is
0.7 mA (typical value).
(see Figs 12 and 13) and should have a width of at least one line period. For the detection of a missing pulse, a guard
current value of 1 mA during normal operation is sufficient. If the RGB outputs must also be blanked if the guard pulse
lasts longer than the vertical blanking period, the guard current must have a value between 2.6 mA and 3.5 mA.
S-correction. The linearity is defined as the ratio of the upper and lower half amplitudes at the vertical output. The
upper amplitude is measured between lines 27 and 167, the lower amplitude between lines 167 and 307 for a 50 Hz
video signal.
a) The incoming V
b) If bus bit VSR = 0, the end of the V
modulator is dimensioned such that 400 A variation in E-W output current of the IC is equivalent to 20% variation
in picture width. In VGA mode, the E-W output current is proportional to the applied line frequency.
a) The flash protection input is used to switch the horizontal drive output off immediately if a picture tube flashover
b) The overvoltage (X-ray) protection is combined with the EHT compensation input. When this protection is
is included in the vertical amplitude control, which controls the vertical scan amplitude between 0.75 and 1.38 of the
C-bus controlled TV display processors
75 and 100% is preferred to be even slower than the rise time from 0 to 75%. This can be realized by activating
bit ESS, at which the total switch-on time of the horizontal output pulse is approximately 1175 ms.
complementary to the start-up behaviour. The switch-off time is approximately 50 ms. The slow-stop procedure
is synchronized to the start of the first new vertical field after reception of the switch-off command. During the
slow-stop period, the fixed beam current switch-off can be activated (see also note 23). This current is active
during a part of the slow stop period, see Fig.15.
on during the flyback pulse. This protection is not active during the switch-on or switch-off period.
pulse. If the synchronized V
HBLNK, then this is field 1. If the synchronized V
CK2H and HBLNK are both output signals of the horizontal divider circuit that is part of the line-locked clock
generator. A reliable field detection is important for correct interlacing and de-interlacing and for the correct timing
of the measurement lines of the black current loop. For the best noise margin, the edges of the V
be on approximately
If VSR = 1, the starting edge is used.
occurs, to protect the line output transistor. An external flash detection circuit is needed. When the flash input is
pulled HIGH, the horizontal output is switched off and status bit FLS is set. When the input turns LOW again, the
horizontal output is switched on immediately without I
activated, the horizontal drive can be directly switched off (via the slow stop procedure). It is also possible to
continue the horizontal drive and only set status bit XPR in output byte 01 of the I
two modes of operation is made via bit PRD.
D
pulse is synchronized with the internal clock signal CK2H that is locked to the incoming H
1
V
4
or the 2f
and
D
3
4
pulse of a field coincides with the internally generated horizontal blanking signal
of the line, referred to the rising edges of the H
V
mode is realized via bit SVF.
D
pulse is used as reference for both field detection and start of vertical scan.
D
pulse does not coincide with HBLNK, then this is field 2. Signals
33
2
C-bus intervention via the slow start procedure.
D
2
input signal.
C-bus. The choice between the
TDA933xH series
on
Preliminary specification
of the output transistor
D
pulse should
D