CY8CPLC10 Cypress Semiconductor, CY8CPLC10 Datasheet

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CY8CPLC10

Manufacturer Part Number
CY8CPLC10
Description
Powerline Communication Solution
Manufacturer
Cypress Semiconductor
Datasheet
www.DataSheet.in
Features
Applications
Cypress Semiconductor Corporation
Document Number: 001-50001 Rev *C
Integrated Powerline Modem PHY
2400 bps Frequency Shift Keying Modulation
Powerline Optimized Network Protocol
Integrates Data Link, Transport, and Network Layers
Supports Bidirectional Half-Duplex Communication
CRC Error Detection to Minimize Data Loss
I
Supports I
Reference Designs for 110V to 240V AC, 12V to 24V AC/DC
Coupling Circuits
Reference Designs Comply with CENELEC EN50065-1:2001
and FCC Part 15
Residential and commercial lighting control
Home automation
Automatic meter reading
Industrial control and signage
Smart energy management
2
Logic Block Diagram
C enabled Powerline Application Layer
2
C Frequencies of 50, 100, and 400 kHz
Host System
Application
External µC
Circuitry
PSoC
198 Champion Court
TM
/
Powerline Communication Solution
I
2
C Packet
Powerline
Functional Overview
The CY8CPLC10 is an integrated Powerline Communication
solution with the Powerline Modem PHY and Powerline Network
Protocol Stack on the same chip. This helps in robust communi-
cation between different nodes on a Powerline.
Powerline Transmitter
The application residing on a host microcontroller generates
messages to be transmitted on the Powerline. These messages
are delivered to the CY8CPLC10 over an I
The Powerline Network Layer residing on the CY8CPLC10
receives these I
ceiver (PLT) packet. These packets are modulated by the FSK
Modem and coupled with Powerline by the external coupling
circuit.
Powerline Receiver
Powerline signals are received by the coupling circuit and
demodulated by the FSK Modem PHY. These PLT packets are
decoded by the Powerline Network Protocol and then transferred
to the external host microcontroller in an I
Powerline Communication Solution
(110V-240V AC, 12V-24V
Powerline Network
AC/DC Powerline
Coupling Circuit
FSK Modem
San Jose
AC/DC, etc.)
Powerline
Protocol
PHY
2
C messages and generates a Powerline Trans-
,
CA 95134-1709
Revised August 21, 2009
2
2
CY8CPLC10
C format.
C serial link.
408-943-2600
[+] Feedback

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CY8CPLC10 Summary of contents

Page 1

... Powerline Transmitter The application residing on a host microcontroller generates messages to be transmitted on the Powerline. These messages are delivered to the CY8CPLC10 over an I The Powerline Network Layer residing on the CY8CPLC10 2 receives these I ceiver (PLT) packet. These packets are modulated by the FSK Modem and coupled with Powerline by the external coupling circuit ...

Page 2

... Figure 2. CY8CPLC10: FSK Modem PHY The physical layer of Cypress’s PLC solution is implemented using an FSK modem that enables half duplex communication on a Powerline. This modem supports raw data rates up to 2400 bps. Figure 3. CY8CPLC10: FSK Modem PHY Block Diagram RX BIU FSK Out TX ...

Page 3

... FSK signal. Coupling Circuit Reference Design The coupling circuit couples low voltage signals from CY8CPLC10 to the Powerline. The topology of this circuit is determined by the voltage on the Powerline and design constraints mandated by Powerline usage regulations. Cypress provides reference designs for a range of Powerline voltages such as 110V AC, 240V AC, 12V DC, 24V DC, and 24V AC ...

Page 4

... Group Membership Group Membership enables the user to multicast messages to select groups. The CY8CPLC10 supports two types of group addressing. Single Group Membership: The Network protocol supports up ■ to 256 different groups on the network in this mode. In this mode, each PLC node can only be part of a single group ...

Page 5

... Document Number: 001-50001 Rev. *D www.DataSheet.in CY8CPLC10 Memory Map Table 3 gives the detailed CY8CPLC10 memory location infor- mation. This information can be used for application devel- opment on an external host controller. Several PLC Commands are instantiated from the Powerline Network Protocol based on which memory location is written. ...

Page 6

... Powerline Note: The registers TX Config, TX Destination Address, TX Command ID and TX Data need to be set before the user sets this bit to Logic 1 5 5-bit value for variable payload length. The payload length can vary from 0 to 31. TX_Configuration Register (0x07) CY8CPLC10 Page [+] Feedback ...

Page 7

... Modem_Config Register (0x31 Logic '0' - 133.3kHz Logic '1' - 131.8kHz 1 - Logic '0' - 133.3kHz Logic '1' - 130.4kHz 600bps 01 - 1200bps 10 - 1800bps 11 - 2400bps (default) TX_Gain Register (0x32) CY8CPLC10 Page [+] Feedback ...

Page 8

... RX_Message_INFO Register (0x40 RX_SA Register (0x41 - 0x48) INT_Status Register (0x69) Note: This register is cleared when the user sets INT_Clear to Logic 0 CY8CPLC10 Description 0000 - 0.008 0001 - 0.012 0010 - 0.020 0011 - 0.027 0100 - 0.039 0101 - 0.055 0110 - 0.078 0111 - 0.109 1000 - 0 ...

Page 9

... Note:The timeout window for receiving Responses Overwrite = Packet is dropped 1- RX Packet is dropped because RX Buffer is full new data available in RX buffer 1- RX buffer has new data available data sent 1- TX data sent successfully CY8CPLC10 Page [+] Feedback ...

Page 10

... PLC chip. Thus the host application can configure the CY8CPLC10, read status and configuration infor- mation, and transmit data to remote Powerline nodes. Refer to the CY8CPLC10 application note (AN52478) on how to build a PLC command set using the CY8CPLC10 memory map. The device has a dedicated pin (I2C_ADDR) for selecting the I slave address while communicating with the external controller ...

Page 11

... Remote node Group Membership Address Byte1- Remote Multiple Group Membership Address Gets the Group Membership of None the Remote node CY8CPLC10 Response (RX Data) If Remote TX Enable = 0, Response = None If Remote TX Enable = 1, Response = Remote PLC Mode register If TX Enable = 0, Response = None If TX Enable = 1, Response = ...

Page 12

... Cypress’s Powerline communication solution easily integrates with wall-switch dimmers and lamp and appliance modules, enabling on and off, dimming, color mixing, and tunable white light control. When operating in master mode, the CY8CPLC10 can control individual or a group of lighting fixtures in a home or a commercial building. Elaborate lighting scenes can be created using application software ...

Page 13

... Smart Energy Management Using the CY8CPLC10, individual panels in a solar array can transmit diagnostic data over the existing DC powerlines. An Array Diagnostic Unit Controller can communicate with individual solar panels to have specific diagnostic information probed. When the diagnostic data is collected by the controller transmitted across the Powerline to a data monitoring console. This makes it possible to acquire and transmit real time data regarding energy output of individual panels to the array controller and subsequently even to a solar farm control station over the Powerline ...

Page 14

... One solution is to reduce the number of cables by using existing Powerline as the transmission medium of digital control signals. The CY8CPLC10 enables control of Automotive LED strobe, beacon, tail lights, and indicators over the existing direct current (DC) 12V to 42V battery Powerline. Combined with Cypress’s EZ-Color lighting solution, dimming and color mixing of LED based automotive lighting fixtures in applications such as mobile LED displays is possible ...

Page 15

... RX_LED FSK_OUT 4 CLKSEL 5 TX_SHUTDOWN 6 LOG_ADDR_0 7 LOG_ADDR_1 8 LOG_ADDR_2 I2C_SCL 11 I2C_SDA 12 XTAL_STABILITY 13 XTAL_IN 14 Vss 15 XTAL_OUT Document Number: 001-50001 Rev. *D www.DataSheet.in Figure 10. CY8CPLC10 28-Pin SSOP RX_LED FSK_OUT 3 CLKSEL 4 TX_SHUTDOWN 5 LOG_ADDR_0 6 LOG_ADDR_1 7 LOG_ADDR_2 I2C_SCL 10 I2C_SDA 11 XTAL_STABLITY 12 XTAL_IN 13 VSS 14 I/O Output RX Indicator LED ...

Page 16

... Logic ‘1’ - Slave Address ‘0x7F’ This is an inverted pin i.e. applying a high voltage on this pin corresponds to writing a logic ‘0’ and vice versa. Input Analog FSK Input.This is the input signal from the Powerline. Power Supply Voltage. 5V ± 10% CY8CPLC10 Description Page [+] Feedback ...

Page 17

... Electrical Specifications This chapter presents the DC and AC electrical specifications of the CY8CPLC10 PLC device. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at Specifications are valid for -40 The following table lists the units of measure that are used in this chapter. ...

Page 18

... Vdd - 1.0 – – – – – 2.1 – – 60 – 1 – 3.5 – 3.5 CY8CPLC10 Max Units Notes o + +100 C The temperature rise from ambient to junction is package specific. See Thermal Impedances.The user must limit the power consumption to comply with this requirement. Max Units Notes 5 ...

Page 19

... Description Min 10 10 Figure 11. I/O Timing Diagram 90% GPIO Pin Output Voltage 10% TRiseF TRiseS CY8CPLC10 Typ Max Units Notes – kHz Accuracy is capacitor and crystal dependent. 50% duty cycle. 250 500 ms 300 600 ms The crystal oscillator frequency is within 100 ppm of ...

Page 20

... Document Number: 001-50001 Rev. *D www.DataSheet. SDA and SCL Pins Standard Mode Description Min Max 0 100 4.0 4.7 4.0 4.7 0 250 4.0 4.7 – T SUDATI2C SUSTAI2C HIGHI2C CY8CPLC10 Fast Mode Units Min Max 0 400 kHz μs – 0.6 – μs – 1.3 – μs – 0.6 – μs – 0.6 – μs – ...

Page 21

... Packaging Information This section illustrates the packaging specifications for the CY8CPLC10 PLC device, along with the thermal impedances for the package and the typical package capacitance on crystal pins. Thermal Impedances Table 15. Thermal Impedances per Package Package 28 SSOP Solder Reflow Peak Temperature Following is the minimum solder reflow peak temperature to achieve good solderability ...

Page 22

... Evaluation Tools CY3272-PLC HV Evaluation Kit The CY3272-PLC is for evaluating, prototyping, and devel- opment with the CY8CPLC10. The I to develop applications on an external micro in order to commu- nicate over Powerline. The hardware comprises of the High Voltage coupling circuit for 110V AC to 230V AC Powerline which is compliant with the CENELEC/FCC standards ...

Page 23

... Build a PSoC Emulator into Your Board For details on emulating the circuit before going to volume pro- duction using an on-chip debug (OCD) non-production PSoC device, see Application Note “Debugging - Build a PSoC Emulator into Your Board http://www.cypress.com/design/AN2323. CY8CPLC10 - AN2323” at Page [+] Feedback ...

Page 24

... Ordering Information The following table lists the CY8CPLC10 PLC device’s key package features and ordering codes. Table 18. CY8CPLC10 PLC Device Key Features and Ordering Information Package 28-Pin (210 Mil) SSOP CY8CPLC10-28PVXI 28-Pin (210 Mil) SSOP CY8CPLC10-28PVXIT (Tape and Reel) Ordering Code Definitions PLC xxx Document Number: 001-50001 Rev ...

Page 25

... Document History Page Document Title: CY8CPLC10 Powerline Communication Solution Document Number: 001-50001 Orig. of Rev. ECN No. Change ** 2606671 GHH/PYRS *A 2662761 GHH/AESA *B 2748542 GHH/PYRS *C 2752799 GHH *D 2754780 GHH/PYRS Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress ...

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