HT45R06 Holtek Semiconductor, HT45R06 Datasheet
HT45R06
Related parts for HT45R06
HT45R06 Summary of contents
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... RAM · Supports PFD for sound generation General Description The HT45R06 is an 8-bit high performance, RISC archi- tecture microcontroller devices specifically designed for cost-effective multiple I/O control product applications. The advantages of low power consumption, I/O flexibil- ity, timer functions, oscillator options, watchdog timer, Rev ...
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... Block Diagram Pin Assignment Rev. 1.00 2 HT45R06 May 24, 2005 ...
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... Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil- ity. Rev. 1.00 Description +6.0V Storage Temperature ............................ 125 C SS +0.3V Operating Temperature........................... HT45R06 May 24, 2005 ...
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... No load, system HALT load, system HALT 0.9V DD LVR enabled 2 =0. =0. HT45R06 Ta=25 C Typ. Max. Unit 5.5 V 5.5 V 5.5 V 0.5 1 100 150 A 200 300 0. 0.4V ...
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... Reset conditions occur, when f = 455kHz and SYS RES connect VDD HT45R06 Ta=25 C Typ. Max. Unit 455 kHz 1000 kHz 2000 kHz 455 kHz 1000 kHz 2000 kHz 455 kHz 1000 kHz 2000 kHz 90 180 s 65 ...
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... Program Counter Program Counter S9~S0: Stack register bits @7~@0: PCL bits 6 HT45R06 * May 24, 2005 ...
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... These areas may function as normal program memory depending upon the requirements. Program Memory Table Location * Table Location P9, P8: Current program counter bits 7 HT45R06 * May 24, 2005 ...
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... Writing indirectly results in no operation. The memory pointer register MP (01H 7-bit register. The bit undefined and reading will return the result ²1². Any writing operation to MP will only transfer the lower 7-bit data to MP. 8 HT45R06 May 24, 2005 ...
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... Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the con- tents should be saved in advance. Function Status (0AH) Register 9 HT45R06 May 24, 2005 ...
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... RETI aged once the CALL operates in the interrupt subrou- tine. Oscillator Configuration There are two oscillator circuits in the microcontroller. System Oscillator 10 HT45R06 Priority Vector 1 04H 2 08H 3 0CH ...
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... WDT. In the case that CLR WDT1 and CLR WDT2 are chosen (i.e. CLRWDT times equal two), these two instructions must be executed to clear the WDT, otherwise, the WDT may reset the chip as a result of time-out. Watchdog Timer 11 HT45R06 May 24, 2005 ...
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... TO flags, the program can distinguish between different chip resets . TO PDF RESET Conditions 0 0 RES reset during power- RES reset during normal operation 0 1 RES wake-up HALT 1 u WDT time-out during normal operation 1 1 WDT wake-up HALT Note: u means unchanged 12 HT45R06 May 24, 2005 ...
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... HT45R06 000H Disable Clear Clear. After master reset, WDT begins counting Input mode Points to the top of the stack RES Reset WDT Time-out (HALT) (HALT)* -uuu uuuu ...
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... The timer/event counter over- flow is one of the wake-up sources. No matter what the clock. operation mode is, writing ETI can disable the in- terrupt service. Function /1 SYS /2 SYS /4 SYS /8 SYS /16 SYS /32 SYS /64 SYS /128 SYS TMRC (0EH) Register 14 HT45R06 May 24, 2005 ...
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... If the control register bit the contents of the latches will move to the inter- nal bus. The latter is possible in the read-modify-write instruction. For output function, CMOS is the only configuration. These control registers are mapped to locations 13H, 15H and 19H. Input/Output Ports 15 HT45R06 May 24, 2005 ...
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... START should remain at 0 until the EOCB is cleared to 0 (end of A/D conversion). The bit 7 of the ACSR is used for testing purposes only. It cannot be used by the users. The bit1 and bit0 of the ACSR are used to select the A/D clock sources. Function ACSR (23H) Register 16 HT45R06 May 24, 2005 ...
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... When the A/D conversion is completed, the A/D interrupt request flag is set. The EOCB bit is set to 1 when the START bit is set from Bit7 Bit6 Bit5 Note: D0~D7 is A/D conversion result data bit LSB~MSB. Rev. 1.00 Function ADCR (22H) Register Bit4 Bit3 Bit2 ADR (21H) Register A/D Conversion Timing 17 HT45R06 Bit1 Bit0 D1 D0 May 24, 2005 ...
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... ADR register mov adr_buffer,a ; save result to user defined register clr ADCR.7 set ADCR.7 ; reset A/D clr ADCR.7 ; start A/D mov a,a_buffer ; restore ACC from temporary storage reti Rev. 1. the A/D clock SYS /8 as the A/D clock SYS 18 HT45R06 May 24, 2005 ...
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... Pull-high resistors (PA, PB and PD): none or pull-high 7 PFD function: enable or disable 8 PA0~PA7 wake-up: enable or disable Rev. 1.00 The relationship between V Note the voltage range for proper chip opera- OPR tion at 2MHz system clock. Low Voltage Reset Options /4 SYS 19 HT45R06 and V is shown below. DD LVR May 24, 2005 ...
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... RES to high. * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. Rev. 1.00 C1 25pF 10k 35pF 27k 300pF 9.1k 300pF 10k 300pF 10k 20 HT45R06 May 24, 2005 ...
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... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.00 Description 21 HT45R06 Instruction Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV 1 Z,C,AC,OV (1) 1 ...
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... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 Description 22 HT45R06 Instruction Flag Cycle Affected 2 None (2) 1 None ...
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... Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO Rev. 1.00 PDF PDF PDF PDF PDF HT45R06 May 24, 2005 ...
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... Program Counter+1 Program Counter Affected flag(s) TO CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO Rev. 1.00 PDF PDF PDF addr PDF PDF HT45R06 May 24, 2005 ...
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... Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO Rev. 1.00 PDF PDF PDF PDF PDF HT45R06 May 24, 2005 ...
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... Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO Rev. 1.00 PDF (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C=C PDF PDF PDF HT45R06 May 24, 2005 ...
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... Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TO Rev. 1.00 Program Counter+1 PDF PDF PDF addr PDF PDF HT45R06 May 24, 2005 ...
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... Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO Rev. 1.00 PDF PDF Program Counter+1 PDF PDF PDF PDF HT45R06 May 24, 2005 ...
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... The contents of the data memory remain unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) TO Rev. 1.00 Stack PDF Stack PDF Stack PDF PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF HT45R06 May 24, 2005 ...
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... Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO Rev. 1.00 PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF PDF PDF PDF HT45R06 May 24, 2005 ...
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... Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO Rev. 1.00 PDF PDF PDF ([m] 1) PDF ([m] 1) PDF HT45R06 May 24, 2005 ...
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... Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO Rev. 1.00 PDF PDF ([m]+1) PDF ([m]+1) PDF PDF HT45R06 May 24, 2005 ...
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... The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO Rev. 1.00 PDF PDF PDF [m].7~[m].4 PDF [m].7~[m].4 [m].3~[m].0 PDF HT45R06 May 24, 2005 ...
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... TBLH directly. Note that this instruction is not valid for HT48R05A-1/HT48C05 Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO Rev. 1.00 PDF PDF PDF PDF PDF HT45R06 May 24, 2005 ...
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... Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO Rev. 1.00 PDF PDF PDF HT45R06 May 24, 2005 ...
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... Package Information 18-pin DIP (300mil) Outline Dimensions Symbol Rev. 1.00 Dimensions in mil Min. Nom. 895 240 125 125 16 50 100 295 335 0 36 HT45R06 Max. 915 260 135 145 20 70 315 375 15 May 24, 2005 ...
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... SOP (300mil) Outline Dimensions Symbol Rev. 1.00 Dimensions in mil Min. Nom. 394 290 14 447 HT45R06 Max. 419 300 20 460 104 May 24, 2005 ...
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... SSOP (150mil) Outline Dimensions Symbol Rev. 1.00 Dimensions in mil Min. Nom. 228 150 8 335 HT45R06 Max. 244 158 12 347 May 24, 2005 ...
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... Key Slit Width T1 Space Between Flange T2 Reel Thickness SSOP 20S (150mil) Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.00 Dimensions in mm 330 1.0 62 1.5 13.0+0.5 0.2 2.0 0.5 24.8+0.3 0.2 30.2 0.2 Dimensions in mm 330 1 62 1.5 13+0.5 0.2 2 0.5 16.8+0.3 0.2 22.2 0.2 39 HT45R06 May 24, 2005 ...
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... Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.00 Dimensions in mm 24.0+0.3 0.1 16.0 0.1 1.75 0.1 11.5 0.1 1.5 0.1 1.5+0.25 4.0 0.1 2.0 0.1 10.9 0.1 12.0 0.1 2.8 0.1 0.3 0.05 21.3 Dimensions in mm 16+0.3 0.1 8 0.1 1.75 0.1 7.5 0.1 1.5+0.1 1.5+0.25 4 0.1 2 0.1 6.5 0.1 9 0.1 2.3 0.1 0.3 0.05 13.3 40 HT45R06 May 24, 2005 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 41 HT45R06 May 24, 2005 ...