HT45R06 Holtek Semiconductor, HT45R06 Datasheet - Page 10

• Manufacturer Part Number: HT45R06
• Description: A/D Type 8-Bit OTP MCU
• Manufacturer: Holtek Semiconductor

External interrupts are triggered by a high to low transi-
tion of the INT and the related interrupt request flag (EIF;
bit 4 of the INTC) will be set. When the interrupt is en-
abled, the stack is not full and the external interrupt is
active, a subroutine call to location 04H will occur. The
interrupt request flag (EIF) and EMI bits will be cleared
to disable other interrupts.
The internal timer/event counter interrupt is initialized by
setting the timer/event counter interrupt request flag
(TF; bit 5 of the INTC), caused by a timer overflow.
When the interrupt is enabled, the stack is not full and
the TF bit is set, a subroutine call to location 08H will oc-
cur. The related interrupt request flag (TF) will be reset
and the EMI bit cleared to disable further interrupts.
The A/D converter end-of-conversion interrupt is initial-
ized by setting the A/D end-of-conversion interrupt re-
quest flag (bit 6 of the INTC), caused by an end of A/D
conversion. When the interrupt is enabled, the stack is
not full and the end of A/D conversion interrupt request
flag is set, a subroutine call to location 00CH will occur.
The related interrupt request flag will be reset and the
EMI bit cleared to disable further interrupts.
During the execution of an interrupt subroutine, other in-
terrupt acknowledge are held until the
instruction is executed or the EMI bit and the related in-
terrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, RET or RETI
may be invoked. RETI will set the EMI bit to enable an
interrupt service, but RET will not.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Rev. 1.00
Bit No.
0
1
2
3
4
5
6
7
Label
EADI
ADF
EMI
EEI
ETI
EIF
TF
Controls the master (global) interrupt (1=enable; 0=disable)
Controls the external interrupt (1=enable; 0=disable)
Controls the timer/event counter interrupt (1=enable; 0=disable)
Controls the A/D converter interrupt (1=enable; 0=disable)
External interrupt request flag (1=active; 0=inactive)
Internal timer/event counter request flag (1=active; 0=inactive)
A/D converter request flag (1=active; 0=inactive)
Unused bit, read as 0
INTC (0BH) Register
RETI
10
The timer/event counter interrupt request flag (TF), ex-
ternal interrupt request flags (EIF), A/D converter inter-
rupt request flag (ADF), enable timer/event counter
interrupt bit (ETI), enable A/D converter interrupt
(EADI), enable external interrupt (EEI) and enable mas-
ter interrupt bit(EMI) constitute the interrupt control reg-
isters (INTC) which is located at 0BH in the data
memory. EMI, EEI, ETI, EADI and are used to control
the enabling/disabling of interrupts. These bits prevent
the requested interrupts from being serviced. Once the
interrupt request flags (TF, EIF, ADF) are set, they will
remain in the INTC register until the interrupts are ser-
viced or cleared by a software instruction.
It is recommended that a program does not use the
rupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only
one stack is left and enabling the interrupt is not well
controlled, the original control sequence will be dam-
aged once the CALL operates in the interrupt subrou-
tine.
Oscillator Configuration
There are two oscillator circuits in the microcontroller.
CALL subroutine within the interrupt subroutine. Inter-
External Interrupt
Timer/Event Counter Overflow
A/D Converter Interrupt
Function
Interrupt Source
System Oscillator
Priority
1
2
3
HT45R06
May 24, 2005
Vector
0CH
04H
08H