HT45R06 Holtek Semiconductor, HT45R06 Datasheet - Page 11

• Manufacturer Part Number: HT45R06
• Description: A/D Type 8-Bit OTP MCU
• Manufacturer: Holtek Semiconductor

Both are designed for system clocks, namely the RC os-
cillator and the Crystal oscillator, which are determined
by the options. No matter what oscillator type is se-
lected, the signal provides the system clock. The HALT
mode stops the system oscillator and ignores an exter-
nal signal to conserve power.
If an RC oscillator is used, an external resistor between
OSC1 and VSS is required and the resistance must
range from 30k
by 4, is available on OSC2, which can be used to syn-
chronize external logic. The RC oscillator provides the
most cost effective solution. However, the frequency of
oscillation may vary with VDD, temperatures and the
chip itself due to process variations. It is, therefore, not
suitable for timing sensitive operations where an accu-
rate oscillator frequency is desired.
If the Crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift required for the oscillator, and no other external
components are required. Instead of a crystal, a
resonator can also be connected between OSC1 and
OSC2 to get a frequency reference, but two external
capacitors in OSC1 and OSC2 are required (if the
oscillating frequency is less than 1MHz).
The WDT oscillator is a free running on-chip RC oscilla-
tor, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDT oscillator still works with a
period of approximately 65 s@5V. The WDT oscillator
can be disabled by options to conserve power.
Oscillator Control Register - OSCC
The QOSC is a control bit for system quick start-up os-
cillation. The QOSC default setting is enabled. After sys-
tem start-up is finished, the QOSC must be cleared by
user to reduce power consumption.
Rev. 1.00
1~7
No.
Bit
0
QOSC
Label
System quick start-up oscillation
0=Disable
1=Enable (Default setting)
Unused bit, read as 0
OSCC (09H) Register
to 750k . The system clock, divided
Function
Watchdog Timer
11
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (sys-
tem clock divided by 4) determined by options. This
timer is designed to prevent a software malfunction or
sequence jumping to an unknown location with unpre-
dictable results. The watchdog timer can be disabled by
option. If the watchdog timer is disabled, all executions
related to the WDT result in no operation.
Once the internal WDT oscillator (RC oscillator with a
period of 65 s at 5V normally) is selected, it is first di-
vided by 2
proximately 5.1s at 5V. This time-out period may vary
with temperature, VDD and process variations. By in-
voking the WDT, prescaler, longer time-out periods can
be realized. If the WDT oscillator is disabled, the WDT
clock may still come from the instruction clock and oper-
ates in the same manner except that in the HALT state
the WDT may stop counting and lose its protecting pur-
pose. In this situation the logic can only be restarted by
external logic.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT will stop the system clock.
The WDT overflow under normal operation will initialize
a chip reset and set the status bit TO . But in the
HALT mode, the overflow will initialize a warm reset ,
and only the Program Counter and SP are reset to zero.
To clear the WDT contents (including the WDT
prescaler), three methods are adopted; external reset (a
low level to RES), software instruction and a HALT in-
struction. The software instructions include CLR WDT
and the other set
these two types of instruction, only one can be active de-
pending on the option
tion . If the CLR WDT is selected (i.e. CLRWDT times
equal one), any execution of the CLR WDT instruction
will clear the WDT. In the case that CLR WDT1 and
two), these two instructions must be executed to clear
the WDT, otherwise, the WDT may reset the chip as a
result of time-out.
CLR WDT2 are chosen (i.e. CLRWDT times equal
16
to get the nominal time-out period of ap-
CLR WDT1 and CLR WDT2 . Of
CLR WDT times selection op-
HT45R06
May 24, 2005