IDT72413L25SO IDT, Integrated Device Technology Inc, IDT72413L25SO Datasheet - Page 4

• Manufacturer Part Number: IDT72413L25SO
• Description: IC FIFO PAR W/FLAGS 32KB 20SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72413L25SO

• Function: Asynchronous
• Memory Size: 32K
• Data Rate: 25MHz
• Access Time: 25ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72413L25SO

AC TEST CONDITIONS
FUNCTIONAL DESCRIPTION:
as opposed to the traditional shift register approach. This FIFO architecture has
a write pointer, a read pointer and control logic, which allow simultaneous read
and write operations. The write pointer is incremented by the falling edge of the
Shift In (Sl) control; the read pointer is incremented by the falling edge of the Shift
Out (SO). The Input Ready (IR) signals when the FIFO has an available
memory location; Output Ready (OR) signals when there is valid data on the
output. Output Enable (OE) provides the capability of three-stating the FIFO
outputs.
FIFO RESET
This causes the FIFO to enter an empty state signified by Output Ready (OR)
being LOW and Input Ready (IR) being HIGH. In this state, the data outputs
(Q
DATA INPUT
input data into the first word location of the FIFO and causes the lnput Ready
(IR) to go LOW. On the HlGH-to-LOW transition of SI, the write pointer is moved
to the next word position and lR goes HlGH indicating the readiness to accept
new data. If the FIFO is full, IR will remain LOW until a word of data is shifted
out.
IDT72413 CMOS PARALLEL FIFO WITH FLAGS
64 x 5
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
The IDT72413, 65 x 5 FIFO is designed using a dual-port RAM architecture
0
The FIFO must be reset upon power up using the Master Reset (MR) signal.
Data is shifted in on the LOW-to-HIGH transition of Shift In (Sl). This loads
-
4
) will be LOW.
GND to 3.0V
See Figure 1
1.5V
1.5V
3ns
2748 tbl 07
4
OUTPUT
RESISTOR VALUES FOR
STANDARD TEST LOAD
DATA OUTPUT
the internal read pointer to be advanced to the next word location. If data is
present, valid data will appear on the outputs and Output Ready (OR) will go
HIGH. If data is not present, OR will stay LOW indicating the FIFO is empty. The
last valid word read from the FIFO will remain at the FlFOs output when it is empty.
When the FIFO is not empty OR goes LOW on the LOW-to-HlGH transition of
SO.
FALL-THROUGH MODE
empty FIFO. After the fall-through delay the data propagates to the output. When
the data reaches the output, the Output Ready (OR) goes HIGH.
data is shifted out of the full FIFO a location is available for new data. After a fall-
through delay, the lnput Ready goes HlGH. If Shift In is HIGH, the new data
can be written to the FIFO. The fall-through delay of a RAM-based FIFO (one
clock cycle) is far less than the delay of a Shift register-based FIFO.
SIGNAL DESCRIPTIONS:
INPUTS:
DATA INPUT (D
STANDARD TEST LOAD
Data is shifted out on the HIGH-to-LOW transition of Shift Out (SO). This causes
The FIFO operates in a Fall-Through Mode when data gets shifted into an
A Fall-Through Mode also occurs when the FIFO is completely full. When
Data input lines. The IDT72413 has a 5-bit data input.
R2
or equivalent circuit
24mA
12mA
8mA
5V
I
OL
R1
TEST POINT
0
-
4
)
*Including scope and jig
30pF*
Figure 1. Output Load
COMMERCIAL TEMPERATURE RANGE
200Ω
390Ω
600Ω
R1
30pF*
DESIGN TEST LOAD
1200Ω
300Ω
760Ω
5V
R2
2K‰
2748 drw 03