IDT72413L25SO IDT, Integrated Device Technology Inc, IDT72413L25SO Datasheet
IDT72413L25SO
Specifications of IDT72413L25SO
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IDT72413L25SO Summary of contents
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FEATURES: • First-ln/First-Out Dual-Port memory—45MHz • organization • Low-power consumption — Active: 200mW (typical) • RAM-based internal structure allows for fast fall-through time • Asynchronous and simultaneous read and write • Expandable by bit width • Cascadable ...
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IDT72413 CMOS PARALLEL FIFO WITH FLAGS PIN CONFIGURATION GND 10 PLASTIC DIP (P20-1, ORDER ...
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IDT72413 CMOS PARALLEL FIFO WITH FLAGS OPERATING CONDITIONS (Commercial 5.0V ± 10 0°C to +70° Symbol Parameter (1) t Shift in HIGH Time SIH (1) t Shift in LOW TIme SIL ...
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IDT72413 CMOS PARALLEL FIFO WITH FLAGS TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load FUNCTIONAL DESCRIPTION: The IDT72413 FIFO is designed using a dual-port ...
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IDT72413 CMOS PARALLEL FIFO WITH FLAGS CONTROLS: SHIFT IN (SI) Shift In controls the input of the data into the FIFO. When SI is HIGH, data can be written to the FIFO via the D0-4 lines. The ...
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IDT72413 CMOS PARALLEL FIFO WITH FLAGS ( (1) INPUT DATA NOTES: 1. FIFO is initially full pulse is applied held HIGH soon as IR becomes HIGH the ...
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IDT72413 CMOS PARALLEL FIFO WITH FLAGS (1) NOTE: 1. FIFO initailly empty (1) MRIRL IR t (1) MRORL MRQ DATA OUTPUTS AF/E NOTE: 1. FIFO ...
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IDT72413 CMOS PARALLEL FIFO WITH FLAGS SIH SI t HFH ( NOTE: 1. FIFO contains 55 words (one short of Almost-Full). t SIH SI t HFH ( NOTE: 1. FIFO contains 31 ...
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IDT72413 CMOS PARALLEL FIFO WITH FLAGS OUTPUT ENABLE COMPOSITE INPUT READY NOTE: 1. FIFOs are expandable in width. However, in forming wider words two external gates are required to generate composite Input and Output Ready flags. This ...
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SHIFT IN SI INPUT READY DATA NOTE: 1. FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing ...