IDT72413L25SO IDT, Integrated Device Technology Inc, IDT72413L25SO Datasheet - Page 5

• Manufacturer Part Number: IDT72413L25SO
• Description: IC FIFO PAR W/FLAGS 32KB 20SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72413L25SO

• Function: Asynchronous
• Memory Size: 32K
• Data Rate: 25MHz
• Access Time: 25ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72413L25SO

CONTROLS:
SHIFT IN (SI)
can be written to the FIFO via the D0-4 lines. The data has to meet set-up and
hold time requirements with respect to the rising edge of SI.
SHIFT OUT (SO)
MASTER RESET (MR)
FIFO should be cleared with a Master Reset. Master Reset is active LOW.
HALF-FULL FLAG (HF)
INPUT READY (IR)
to it. When IR is LOW, the FIFO is unavailable for new input data, IR is also
used to cascade many FIFOs together, as shown in Figure 13.
NOTES:
1. IR HIGH indicates space is available and a SI pulse may be applied.
2. Input Data is loaded into the FIFO.
3. IR goes LOW indicating the FIFO is unavailable for new data.
4. The write pointer is incremented.
5. The FIFO is ready for the next word.
6. If the FIFO is full, then IR remains LOW.
7. SI pulses applied while IR is LOW will be ignored (see Figure 4).
IDT72413 CMOS PARALLEL FIFO WITH FLAGS
64 x 5
INPUT DATA
Shift In controls the input of the data into the FIFO. When SI is HIGH, data
Shift Out controls the outputs data from the FIFO.
Master Reset clears the FIFO of any data stored within. Upon power up, the
Half-Full Flag signals when the FIFO has 32 or more words in it.
When Input Ready is HIGH, the FIFO is ready for new input data to be written
INPUT DATA
IR
SI
IR
SI
(7)
t
IDS
(1)
(2)
t
SIH
STABLE DATA
t
IDH
Figure 3. The Machanism of Shifting Data Into the FIFO
1/f
IN
t
SIL
(3)
Figure 2. Input Timing
5
OUTPUT READY (OR)
OR is LOW, the FIFO is unavailable for new output data. OR is also used to
cascade many FIFOs together, as shown in Figure 13.
OUTPUT ENABLE (OE)
LOW.
ALMOST-FULL/EMPTY FLAG (AF/E)
or 1/8 from empty (8 or less words).
OUTPUTS:
DATA OUTPUT (Q
When Output Ready is HIGH, the output (Q
Output Enable is used to enable the FIFO outputs onto a bus. OE is active
Almost-Full/Empty Flag signals when the FIFO is 7/8 full (56 or more words)
Data output lines, three-state. The IDT72413 has a 5-bit output.
0
-
4
)
COMMERCIAL TEMPERATURE RANGE
0
-
4
) contains valid data. When