DS2415 Dallas Semiconducotr, DS2415 Datasheet
DS2415
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DS2415 Summary of contents
Page 1
... OVERVIEW The DS2415 has two main data components: 1) 64-bit lasered ROM, and 2) real time clock counter (Figure 1). The real time clock utilizes an on-chip oscillator that is connected to an external 32.768 kHz crystal. All data is read and written least significant bit first. The real time clock functions will not be available until the ROM function protocol has been established ...
Page 2
... BLOCK DIAGRAM Figure 1 64-BIT LASERED ROM Each DS2415 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. (See Figure 3.) ...
Page 3
... The functions required to exercise the control functions of the DS2415 are not accessible until the ROM function protocol has been satisfied. This protocol is described in the ROM functions flow chart (Figure 7). The 1-Wire bus master must first provide one of the four ROM function commands. After a ROM function sequence has been successfully executed, the bus master may then provide one of the function commands specific to the DS2415 (Figure 5) ...
Page 4
... The “Clock Function Flow Chart” (Figure 5) describes the protocols necessary for accessing the real time clock. With only 4 bytes of real time clock and one control byte the DS2415 does not provide random access. Reading and writing always starts with the device control byte followed by the least significant byte of the time data ...
Page 5
... After this the bus master may continue reading from the DS2415. The data received will be the same as in the first pass through the command flow. The Read Clock command can be ended at any point by issuing a Reset Pulse ...
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... CLOCK FUNCTION COMMAND FLOW CHART Figure DS2415 ...
Page 7
... MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 120 s, one or more of the devices on the bus may be reset. Since the DS2415 gets all its energy for operation through its V for an extended time period ...
Page 8
... This command allows the bus master to read the DS2415s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can only be used if there is a single DS2415 on the bus. If more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-AND result) ...
Page 9
... ROM FUNCTIONS FLOW CHART Figure DS2415 ...
Page 10
... DS2415. During write time slots, the delay circuit determines when the DS2415 will sample the data line. For a read data time slot transmitted, the delay circuit determines how long the DS2415 will hold the data line low overriding the 1 generated by the master. If the data bit the device will leave the read data time slot unchanged ...
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... READ/WRITE TIMING DIAGRAM Figure 9 Write-1 Time Slot Write-0 Time Slot < 120 s SLOT < LOW1 < REC < t < 120 s LOW0 SLOT < REC DS2415 ...
Page 12
... Read-data Time Slot RESISTOR MASTER DS2415 CRYSTAL PLACEMENT ON PCB Figure 10 LOCAL GROUND PLANE BENEATH SIGNAL PLANE OR ON OTHER SIDE OF PCB < 120 s SLOT < LOWR 0 t < RELEASE < REC RDV t < DS2415 ...
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... Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. The Dallas Semiconductor DS2415 is built to the highest quality standards and manufactured for long term reliability. All Dallas Semiconductor devices are made using the same quality materials and manufacturing methods ...
Page 14
... REC t 480 RSTH t 480 RSTL t 15 PDH t 60 PDL may have to be reduced to as much as 0.5V to always IL1MAX 2.5V to 5.5V) BAT TYP MAX UNITS 120 120 exactly 960 240 s DS2415 NOTES ...