AN1627 Freescale Semiconductor / Motorola, AN1627 Datasheet - Page 18

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AN1627

Manufacturer Part Number
AN1627
Description
Low Cost High Efficiency Sensorless Drive for Brushless dc Motor Using MC68HC (7)05MC4
Manufacturer
Freescale Semiconductor / Motorola
Datasheet
The IC Interrupt (ICIE2) is disabled here to preserve the Back-EMF detection from the disturbances
produced during the commutation (see Figure 5-3.). It is enabled again after approximately 50
If these two events are going to happen closer than 133
commutation is performed at the right moment (no speed variation) while the A/D conversion is
postponed by 256
A new value for the Timer Output Compare Register (OCRH/L) is calculated, based on the states of
Timer1 and Timer2.
5.2.5.2
The signal generated by the Position Recognition Logic causes this interrupt. Special care must be
taken due to noise, which can disturb the incoming signal. The respective pin (TCAP2) is sampled in
suitable places within the BODY and START routines. The period is less than 90
When this ISR is initiated, then another three samples of the TCAP2 are taken and the state of the
TCAP2 pin is then evaluated. Based on the last sample before the ISR is executed, the selected edge
sensitivity (IEDG2) and the samples after ISR is initiated, and the Input Capture event is verified. If it is
acceptable then the captured time is stored in memory and the Input Capture Interrupt ISR is finished.
The captured time is then used to calculate the angle
5.2.5.3
The wake up signal is serviced here. This allows the system to perform communication while the
microcontroller is in the stand-by mode.
5.3
The cycle time of the main routines was measured. The values obtained are given in the following table.
MOTOROLA
18
Routine
ISR-OC
ISR-IC
Timer Input Capture Interrupt Service Routine
IRQ
Program Load
Body
Start
s (see Figure 5-5.).
Figure 5-5.
Freescale Semiconductor, Inc.
For More Information On This Product,
Min.
22
25
55
Measurement Synchronization with PWM
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s
s
s
Cycle time (6MHz clock frequency)
Table 5-1.

in the PLL.
typical
~70
~80
~25
s , then Timer2 obtains priority and the
84
s
s
s
s
s and is typically 30
170
180
Max.
90
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s
s
s
REV 0.2
AN1627
s .
s .

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