IDT72245LB25JI8 IDT, Integrated Device Technology Inc, IDT72245LB25JI8 Datasheet - Page 3

• Manufacturer Part Number: IDT72245LB25JI8
• Description: IC FIFO 1024X18 SYNC 25NS 68PLCC
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72245LB25JI8

• Function: Synchronous
• Memory Size: 18.4K (1K x 18)
• Access Time: 25ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72245LB25JI8

PIN DESCRIPTION
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Symbol
D0–D17
RS
WCLK
WEN
RCLK
REN
OE
LD
FL
WXI
RXI
FF
EF
PAE
PAF
WXO/HF
RXO
Q0–Q17
V
GND
CC
Data Inputs
Reset
Write Clock
Write Enable
Read Clock
Read Enable
Output Enable
Load
First Load
Write Expansion
Read Expansion
Full Flag
Empty Flag
Programmable
Almost-Empty Flag
Programmable
Almost-Full Flag
Write Expansion
Out/Half-Full Flag
Read Expansion
Out
Data Outputs
Power
Ground
Name
I/O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
In the single device or width expansion configuration, FL is grounded. In the depth expansion configuration, FL
Data inputs for a 18-bit bus.
When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF and PAF
go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after power-up.
When WEN is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK, if the FIFO is not full.
When WEN is LOW and LD is HIGH, data is written into the FIFO on every LOW-to-HIGH transition of
WCLK. When WEN is HIGH, the FIFO holds the previous data. Data will not be written into the FIFO if the FF
is LOW.
When REN is LOW, data is read from the FIFO on a LOW-to-HIGH transition of RCLK, if the FIFO is not empty.
When REN is LOW, and LD is HIGH, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.
When REN is HIGH, the output register holds the previous data. Data will not be read from the FIFO if the EF
is LOW.
When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance
state.
When LD is LOW, data on the inputs D0–D11 is written to the offset and depth registers on the LOW-to-HIGH
transition of the WCLK, when WEN is LOW. When LD is LOW, data on the outputs Q0–Q11 is read from the
offset and depth registers on the LOW-to-HIGH transition of the RCLK, when REN is LOW.
is grounded on the first device (first load device) and set to HIGH for all other devices in the Daisy Chain.
In the single device or width expansion configuration, WXI is grounded. In the depth expansion configuration,
WXI is connected to WXO (Write Expansion Out) of the previous device.
In the single device or width expansion configuration, RXI is grounded. In the depth expansion configuration,
RXI is connected to RXO (Read Expansion Out) of the previous device.
When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO
is not full. FF is synchronized to WCLK.
When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is HIGH, the
FIFO is not empty. EF is synchronized to RCLK.
When PAE is LOW, the FIFO is almost empty based on the offset programmed into the FIFO. The default
offset at reset is 31 from empty for IDT72205LB, 63 from empty for IDT72215LB, and 127 from empty for
IDT72225LB/72235LB/72245LB.
When PAF is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default offset at
reset is 31 from full for IDT72205, 63 from full for IDT72215LB, and 127 from full for IDT72225LB/72235LB/
72245LB.
In the single device or width expansion configuration, the device is more than half full when HF is LOW. In the
depth expansion configuration, a pulse is sent from WXO to WXI of the next device when the last location in the
FIFO is written.
In the depth expansion configuration, a pulse is sent from RXO to RXI of the next device when the last
location in the FIFO is read.
Data outputs for an 18-bit bus.
+5V power supply pins.
Eight ground pins for the PLCC and seven gound pins for the TQFP/STQFP.
3
TM
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008