IDT72245LB25JI8 IDT, Integrated Device Technology Inc, IDT72245LB25JI8 Datasheet - Page 7

• Manufacturer Part Number: IDT72245LB25JI8
• Description: IC FIFO 1024X18 SYNC 25NS 68PLCC
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72245LB25JI8

• Function: Synchronous
• Memory Size: 18.4K (1K x 18)
• Access Time: 25ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72245LB25JI8

then a signal at this input can neither increment the write offset register pointer,
nor execute a write.
LD pin is set LOW and REN is set LOW; then, data can be read on the LOW-
to-HIGH transition of the read clock (RCLK). The act of reading the control
registers employs a dedicated read offset register pointer. (The read and write
pointers operate independently).
registers.
FIRST LOAD (FL)
mode. In the Depth Expansion configuration, FL is grounded to indicate it is the
first device loaded and is set to HIGH for all other devices in the Daisy Chain.
(See Operating Configurations for further details.)
WRITE EXPANSION INPUT (WXI)
Device or Width Expansion mode. WXI is connected to Write Expansion Out
(WXO) of the previous device in the Daisy Chain Depth Expansion mode.
READ EXPANSION INPUT (RXI)
Device or Width Expansion mode. RXI is connected to Read Expansion Out
(RXO) of the previous device in the Daisy Chain Depth Expansion mode.
OUTPUTS:
FULL FLAG(FF)
When FF is HIGH, the FIFO is not full. If no reads are performed after a reset,
FF will go LOW after D writes to the FIFO. D = 256 writes for the IDT72205LB,
512 for the IDT72215LB, 1,024 for the IDT72225LB, 2,048 for the IDT72235LB
and 4,096 for the IDT72245LB.
TABLE 1 — STATUS FLAGS
NOTES:
1. n = Empty Offset (Default Values : IDT72205LB n=31, IDT72215LB n = 63, IDT72225LB/72235LB/72245LB n = 127)
2. m = Full Offset (Default Values : IDT72205LB m=31, IDT72215LB m = 63, IDT72225LB/72235LB/72245LB m = 127)
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
129 to (256-(m+1))
When the LD pin is LOW and WEN is HIGH, the WCLK input is disabled;
The contents of the offset registers can be read on the output lines when the
A read and a write should not be performed simultaneously to the offset
FL is grounded to indicate operation in the Single Device or Width Expansion
This is a dual purpose pin. WXI is grounded to indicate operation in the Single
This is a dual purpose pin. RXI is grounded to indicate operation in the Single
When the FIFO is full, FF will go LOW, inhibiting further write operations.
The FF is updated on the LOW-to-HIGH transition of the write clock (WCLK).
(256-m)
(n + 1) to 128
IDT72205LB
1 to n
256
0
(2)
(1)
to 255
257 to (512-(m+1))
(512-m)
(n + 1) to 256
IDT72215LB
1 to n
512
0
(2)
(1)
to 511
Number of Words in FIFO
513 to (1,024-(m+1))
(1,024-m)
(n + 1) to 512
IDT72225LB
1 to n
1,024
0
(2)
(1)
to 1,023
1,025 to (2,048-(m+1))
(2,048-m)
7
(n + 1) to 1,024
IDT72235LB
EMPTY FLAG/ (EF)
When EF is HIGH, the FIFO is not empty.
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
reaches the Almost-Full condition. If no reads are performed after Reset (RS),
the PAF will go LOW after (256-m) writes for the IDT72205LB, (512-m) writes
for the IDT72215LB, (1,024-m) writes for the IDT72225LB, (2,048–m) writes
for the IDT72235LB and (4,096–m) writes for the IDT72245LB. The offset “m”
is defined in the FULL offset register.
31 away from completely full for IDT72205LB, 63 away from completely full for
IDT72215LB, and 127 away from completely full for IDT72225LB/72235LB/
72245LB.
(WCLK). PAF is reset to HIGH on the LOW-to-HIGH transition of the read clock
(RCLK). Thus PAF is asynchronous.
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
pointer is "n+1" locations less than the write pointer. The offset "n" is defined in
the EMPTY offset register.
(PAE) will be LOW when the device is 31 away from completely empty for
IDT72205LB, 63 away from completely empty for IDT72215LB, and 127 away
from completely empty for IDT72225LB/72235LB/72245LB.
(RCLK). PAE is reset to HIGH on the LOW-to-HIGH transition of the write clock
(WCLK). Thus PAE is asynchronous.
WRITE EXPANSION OUT/HALF-FULL FLAG (WXO/HF)
mode, when Write Expansion In (WXI) and Read Expansion In (RXI) are
grounded, this output acts as an indication of a half-full memory.
TM
1 to n
2,048
The ProgrammableAlmost-Empty Flag(PAE) will go LOW when the read
If there is no Empty offset specified, the Programmable Almost-Empty Flag
The PAE is asserted LOW on the LOW-to-HIGH transition of the read clock
This is a dual-purpose output. In the Single Device and Width Expansion
When the FIFO is empty, EF will go LOW, inhibiting further read operations.
The EF is updated on the LOW-to-HIGH transition of the read clock (RCLK).
The Programmable Almost-Full Flag (PAF) will go LOW when FIFO
The PAF is asserted LOW on the LOW-to-HIGH transition of the write clock
If there is no Full offset specified, the PAF will be LOW when the device is
0
(2)
(1)
to 2,047
2,049 to (4,096-(m+1))
(4,096-m)
(n + 1) to 2,048
IDT72245LB
1 to n
4,096
0
(2)
(1)
to 4,095
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FF PAF
H
H
H
H
H
L
OCTOBER 22, 2008
H
H
H
H
L
L
HF
H
H
H
L
L
L
PAE EF
H
H
H
H
L
L
H
H
H
H
H
L