IDT72245LB25JI8 IDT, Integrated Device Technology Inc, IDT72245LB25JI8 Datasheet - Page 6

• Manufacturer Part Number: IDT72245LB25JI8
• Description: IC FIFO 1024X18 SYNC 25NS 68PLCC
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72245LB25JI8

• Function: Synchronous
• Memory Size: 18.4K (1K x 18)
• Access Time: 25ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72245LB25JI8

SIGNAL DESCRIPTIONS:
INPUTS:
DATA IN (D
CONTROLS:
RESET (RS)
During reset, both internal read and write pointers are set to the first location.
A reset is required after power-up before a write operation can take place. The
Full Flag (FF), Half-Full Flag (HF) and Programmable Almost-Full Flag (PAF)
will be reset to HIGH after t
Almost-Empty Flag (PAE) will be reset to LOW after t
register is initialized to all zeros and the offset registers are initialized to their default
values.
WRITE CLOCK (WCLK)
(WCLK). Data setup and hold times must be met with respect to the LOW-to-HIGH
transition of WCLK.
WRITE ENABLE (WEN)
the FIFO RAM array on the rising edge of every WCLK cycle if the device is
not full. Data is stored in the RAM array sequentially and independently of any
ongoing read operation.
cycle.
Upon the completion of a valid read cycle, FF will go HIGH allowing a write to
occur. The FF flag is updated on the rising edge of WCLK. WEN is ignored
when the FIFO is full.
READ CLOCK (RCLK)
Clock (RCLK), when Output Enable (OE) is set LOW.
READ ENABLE (REN)
RAM array into the output register on the rising edge of every RCLK cycle if
the device is not empty.
no new data is loaded into the output register. The data outputs Q
the previous data value.
FIFO, must be requested using REN. When the last word has been read from
the FIFO, the Empty Flag (EF) will go LOW, inhibiting further read operations.
REN is ignored when the FIFO is empty. Once a write is performed, EF will
go HIGH allowing a read to occur. The EF flag is updated on the rising edge
of RCLK.
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Reset is accomplished whenever the Reset (RS) input is taken to a LOW state.
When the WEN input is LOW and LD input is HIGH, data may be loaded into
When WEN is HIGH, no new data is written in the RAM array on each WCLK
To prevent data overflow, FF will go LOW, inhibiting further write operations.
Data inputs for 18-bit wide data.
A write cycle is initiated on the LOW-to-HIGH transition of the Write Clock
The Write and Read Clocks can be asynchronous or coincident.
Data can be read on the outputs on the LOW-to-HIGH transition of the Read
The Write and Read Clocks can be asynchronous or coincident.
When Read Enable is LOW and LD input is HIGH, data is loaded from the
When the REN input is HIGH, the output register holds the previous data and
Every word accessed at Q
0
- D
17
)
RSF
n
. The Empty Flag (EF) and Programmable
, including the first word written to an empty
RSF
. During reset, the output
0
-Q
n
maintain
6
OUTPUT ENABLE (OE)
receive data from the output register. When OE is disabled (HIGH), the Q output
data bus is in a high-impedance state.
LOAD (LD)
tain two 12-bit offset registers with data on the inputs, or read on the outputs.
When the Load (LD) pin is set LOW and WEN is set LOW, data on the inputs
D0-D11 is written into the Empty Offset register on the first LOW-to-HIGH
transition of the Write Clock (WCLK). When the LD pin and (WEN) are held
LOW then data is written into the Full Offset register on the second LOW-to-HIGH
transition of (WCLK). The third transition of the write clock (WCLK) again writes
to the Empty Offset register.
or two offset registers can be written and then by bringing the LD pin HIGH, the
FIFO is returned to normal read/write operation. When the LD pin is set LOW,
and WEN is LOW, the next offset register in sequence is written.
NOTE:
1. The same selection sequence applies to reading from the registers. REN is enabled and
NOTE:
1. Any bits of the offset register not being programmed should be set to zero.
TM
read is performed on the LOW-to-HIGH transition of RCLK.
17
17
When Output Enable (OE) is enabled (LOW), the parallel output buffers
The IDT72205LB/72215LB/72225LB/72235LB/72245LB devices con-
However, writing all offset registers does not have to occur at one time. One
LD
0
0
1
1
Figure 3. Offset Register Location and Default Values
WEN
0
1
0
1
11
11
Figure 2. Write Offset Register
WCLK
001FH (72205) 003FH (72215):
001FH (72205) 003FH (72215):
EMPTY OFFSET REGISTER
007FH (72225/72235/72245)
007FH (72225/72235/72245)
FULL OFFSET REGISTER
DEFAULT VALUE
DEFAULT VALUE
Writing to offset registers:
Empty Offset
Full Offset
No Operation
Write Into FIFO
No Operation
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Selection
OCTOBER 22, 2008
2766 drw 05
0
0