AN2108 Freescale Semiconductor / Motorola, AN2108 Datasheet - Page 17

• Manufacturer Part Number: AN2108
• Description: AN2108 Programming the DSP56307/DSP56311 EFCOP in C Using Taskings Tool Suite
• Manufacturer: Freescale Semiconductor / Motorola

4.2.3 DMA and DSP56300 Core Interaction
4.3 Interrupts
The DSP56300 core sets up the DMA channels. Then the EFCOP processes all of the data samples with no
core intervention, freeing the DSP56300 core to perform other tasks. The DSP56300 core uses two
different ways to check whether all samples have been processed:
In both cases, the DMA channel that is polled or configured to generate an interrupt at the end of the DMA
transfer is normally the channel used to transfer data from the FDOR to memory, since this is the last DMA
transfer to take place.
The third method of transferring data to or from the EFCOP is to set the FDIBE or FDOBF bit of the FCSR
register to generate interrupts. Unlike the DMA, the FDIBE and FDOBF bits do not generate interrupt
requests unless the EFCOP is configured to do so. Interrupt service routines that service the appropriate
interrupt request to perform the data transfer must be written and configured.
The interrupt method of data transfer requires DSP56300 core intervention, since the DSP56300 core must
stop its current activity to service the interrupt request. However, unlike polling, the use of interrupts does
not require the core to wait in a “do-nothing” loop until FDIBE or FDOBF becomes set. The following
steps set up the interrupts for EFCOP data transfers:
1. Set the interrupt mask bits, (bits 8 and 9) in the Status Register (SR). These bits determine which
2. Set the priority levels of the EFCOP (bits 10 and 11 of the Interrupt Priority Register Peripheral
3. Enable interrupt generation bits in the EFCOP status register (FCSR). Setting bit 10 (FDIIE) enables
•
•
priorities of interrupt are masked.
(IPRP)). These priority levels should have a sufficiently high priority that they are not masked by the
interrupt mask priority setting in bits 8 and 9 of the Status Register. Setting the interrupt priority level
is application-dependent since other interrupts may be in use elsewhere in the system.
interrupt generation when the FDIR becomes empty; setting bit 11 (FDOIE) enables interrupt
generation when the FDOR becomes full.
Polling. The DSP56300 core checks the DMA Transfer Done (DTD) bit for the appropriate DMA
channel in the DMA Status Register (DSTR). This bit is cleared (by writing a one to it) when the
DMA transfer completes.
Interrupts. If the DMA Interrupt Enable (DIE) bit is set (bit 22 of the DCRx register), an interrupt
occurs when the DMA transfer completes.
/* DDS
/* DSS
= 00
= 01
Programming the DSP56307/DSP56311 EFCOP in C
Freescale Semiconductor, Inc.
For More Information On This Product,
(Dest (output[]) is in X memory)*/
(Source (FDOR) is in Y memory)*/
Go to: www.freescale.com
Transferring Data to and from the EFCOP
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