AN2148 Motorola / Freescale Semiconductor, AN2148 Datasheet

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... Design Considerations for Interfacing SDRAM with PRELIMINARY MC68VZ328 Application Note Bryan C. Chan AN2148/D Rev. 0, 5/2001 by ...

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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of ...

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Abstract and Contents ™ The MC68VZ328 (DragonBall DRAM controller. This application note will provide information on the setup and use of the DragonBall VZ to access SDRAM. This is a pre-publication draft. This application note will run through all aspects ...

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Design Considerations for Interfacing SDRAM with MC68VZ328 Pre-Publication Draft ...

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Introduction This application note provides information for users who are preparing to use Synchronous DRAM (SDRAM) with the MC68VZ328 (VZ). This document is a pre-publication draft. The following issues are covered in this application note: 1. Physical interface between ...

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Physical Interface Between SDRAM and MC68VZ328 2 Physical Interface Between SDRAM and MC68VZ328 Recommended pin connections between the Dragon Ball VZ to SDRAM are shown below: MC68VZ328 PB5/CSD1/CAS1/SDCS1 PB4/CSD0/CAS0/SDCS0 PM1/SDCE PM0/SDCLK PB2/CSC0/RAS0/SDRAS PB3/CSC1/RAS1/SDCAS PM2/DQMH PM3/DQML PB1/CSB1/SDWE D[0:15] A[1:10] PM4/SDA10 Figure ...

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Below are some examples of address line configuration for different sizes of SDRAM: Table 2. Address Line Configurations (8-bit or 16-bit) SDRAM Pins A[0:9] A[1:10] A10 SDA10 1 A12 A11 A12 X BS0 X BS1 X Note "No ...

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SDRAM Control Registers 3 SDRAM Control Registers This section will cover the relevant registers involved in SDRAM operations. The following registers have an effect on SDRAM operation: Name Address CSGBD 0x(FF)FFF106 CSD 0x(FF)FFF116 CSCTRL1 0x(FF)FFF10A CSCTRL2 0x(FF)FFF10C DRAMMC 0x(FF)FFFC00 DRAMC ...

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SDRAM 0x017FFFFF 0xFFFFFFFF Figure 2. Chip-Select Base Address Register 3.1.2 Chip-Select Register D (CSD) & Chip-Select Control Register 1 (CSCTRL1) The CSD register is used to determines three things: • If chip-select group C will be ...

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SDRAM Control Registers 1 DSIZ3 This bit resides in the CSCTRL1 register. 2) Use this setting for 32MB SDRAM as well. NOTE SDRAM Chip-Select Size For 32MB SDRAM, the chip-select size is first set to ...

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Sample ASB PreC. Act Figure 4. Normal SDRAM Read/Write Sample Early ASB PreC. Act Figure 5. SDRAM Read/Write with ECD Using the PK3/UDS signal as a reference in Figure 4 and Figure 5, setting the ECDD bit can improve SDRAM ...

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SDRAM Control Registers 3.2.1 DRAM Memory Configuration Register (DRAMMC) The DRAM Controller uses address multiplexing to support different types of SDRAM. For recommendations on how address lines should be configured with the SDRAM, follow tables 7-1 through 7-5 in the ...

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The RM bit controls the SDRAM refresh mode between Auto-Refresh and Self-Refresh mode. See section 7.3.2 in the VZ user manual for details on other options. 3.2.3 SDRAM Control Register (SDCTRL) SDRAM control register provides features specific to SDRAM operation. ...

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SDRAM Control Registers Figure 7 depicts the internal structure of the logic. Two multiplexors will derive the bank address based on the setting of the SDCTRL register bits BNKADDH[1:0] and BNKADDL[1:0]. The controller supports 4 banks, therefore there are two ...

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Start SDRAM refresh cycles using the RE bit in the SDCTRL register • Set mode register of the SDRAM with the MR bit ...

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SDRAM Control Registers Figure 10. Precharge Power-down Mode Figure 11. Power-down Mode Disabled 16 Design Considerations for Interfacing SDRAM with MC68VZ328 Refer to Table 1 for signal description Refer to Table 1 for signal description Pre-Publication Draft ...

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SDRAM Initialization Sequences The following are the initialization sequences use by the VZ ADS board: ;*************************************** ; SDRAM 64M-bit, Single Band, Latency 2 ;*************************************** move.w #$0000,GRPBASED move.w #$0281,CSD move.w #$0040,CSCR move.w #$0000,DRAMC move.w #$C03F,SDCTRL move.w #$4020,DRAMMC move.w #$8000,DRAMC clr.w ...

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SDRAM Power Control Features 5 SDRAM Power Control Features The DRAM controller can initiate two kinds of power control features: • Self-refresh mode. • Power-down mode. SDRAM self-refresh mode is controlled by the RE bit in the DRAMC register. By ...

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SDRAM Logic Analyser Captures The following logic analyser captures show SDRAM read and write cycles generated ADS. Sample ASB PreC. Act Figure 13. SDRAM Read/Write; CAS Latency = 1; Page-Miss Condition Figure 14. SDRAM Read; CAS ...

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SDRAM Logic Analyser Captures Figure 15. SDRAM Write; CAS Latency = 1; Page-Hit Condition Sample ASB Figure 16. SDRAM Read/Write; CAS Latency = 2; Page-Miss Condition 20 Design Considerations for Interfacing SDRAM with MC68VZ328 Write Write Act Refer to Table ...

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Read Act Figure 17. SDRAM Read; CAS Latency = 2; Page-Hit Condition Write Figure 18. SDRAM Write; CAS Latency = 2; Page-Hit Condition SDRAM Logic Analyser Captures Pre-Publication Draft DRAM Controller Registers Read Refer to Table 1 for signal description ...

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SDRAM Logic Analyser Captures Sample Early ASB PreC. Act Figure 19. SDRAM Read/Write; CAS Latency = 1; Page-Miss Condition; with ECD Figure 20. SDRAM Read; CAS Latency = 1; Page-Hit Condition; with ECD 22 Design Considerations for Interfacing SDRAM with ...

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Write Act Figure 21. SDRAM Write; CAS Latency = 1; Page-Hit Condition; with ECD Figure 22. LCD DMA Read; CAS Latency = 2; Burst Length = 4 SDRAM Logic Analyser Captures Pre-Publication Draft DRAM Controller Registers Write Refer to Table ...

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SDRAM Logic Analyser Captures 24 Design Considerations for Interfacing SDRAM with MC68VZ328 Pre-Publication Draft ...