AN2148 Motorola / Freescale Semiconductor, AN2148 Datasheet - Page 13

• Manufacturer Part Number: AN2148
• Description: Design Considerations for Interfacing SDRAM with MC68VZ328
• Manufacturer: Motorola / Freescale Semiconductor

The RM bit controls the SDRAM refresh mode between Auto-Refresh and Self-Refresh mode. See section
7.3.2 in the VZ user manual for details on other options.
3.2.3
SDRAM control register provides features specific to SDRAM operation. This section will run through
those features in detail.
The first register bit is the SDEN bit (bit 15) which needs to be set in order for SDRAM to be used. This
bit should be set before the EN bit in the DRAMC to ensure SDRAM support once the controller is
enabled.
Along with the SDEN bit, a few other settings have to be checked as well. This includes the CAS Latency
or CL bit and the Bank Address Line settings (BNKADDH & BNKADDL).
The CAS Latency of a SDRAM should always be set in the SDRAM’s mode register before using the
SDRAM. The DragonBall VZ support CAS latency of 2 or 1 cycle.
The number of SDRAM banks is defined using the BNKADDH and BNKADDL bits. This "bank" refers
to the internal arrangement of the SDRAM chip.
SDRAM Control Register (SDCTRL)
Although most SDRAM does not specify support for CAS latency below
2 clock counts. Testing shows that a number of those SDRAM have no
problems while running in CAS latency 1 mode.
Figure 7. BNKADDH and BNKADDL Model
BNKADDL[1:0]
BNKADDH[1:0]
PA19
PA21
PA23
PA20
PA22
PA24
SDCTRL
SDCTRL
’0’
’0’
NOTE: SDRAM CAS Latency
SDRAM Control Registers
Pre-Publication Draft
00
10
00
10
01
11
01
11
(low bank address)
(high bank address)
bnkaddL
bnkaddh
DRAM Controller Registers
13