AN2148 Motorola / Freescale Semiconductor, AN2148 Datasheet - Page 12

• Manufacturer Part Number: AN2148
• Description: Design Considerations for Interfacing SDRAM with MC68VZ328
• Manufacturer: Motorola / Freescale Semiconductor

SDRAM Control Registers
3.2.1
The DRAM Controller uses address multiplexing to support different types of SDRAM. For
recommendations on how address lines should be configured with the SDRAM, follow tables 7-1 through
7-5 in the DragonBall VZ User Manual.
This register also controls the refresh cycle timing, see section 7.2.3 in the VZ user manual for details. For
typical applications, the default value for the REF bits will suffice.
3.2.2
The DRAMC contains the following features that are relevant to SDRAM operations:
Of these features, the first two options require attention before the SDRAM is initialized.
After the DRAM controller is enabled through the EN bit (bit 15) of the DRAMC, the page size of the
SDRAM should be set in the PGSZ field (bits 9-8). The page size of a particular SDRAM can be found by
the number of column addresses for each bank. The amount of memory space covered by the column
addresses is the page size. For 8-bit SDRAM, the number should be divide by two before applying to the
PGSZ field.
12
Address
12 Row
Example:
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•
•
•
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Master DRAM Controller enable
Page size of SDRAM
SDRAM Refresh mode
Light Sleep option
Reset Burst Refresh option
For 16-bit SDRAM, PGSZ = 00 (256 words)
8 column address = 256 memory space
DRAM Memory Configuration Register (DRAMMC)
DRAM Control Register (DRAMC)
Design Considerations for Interfacing SDRAM with MC68VZ328
64Mbit SDRAM
Address
8 Column
Figure 6. Calculating Page Size
Pre-Publication Draft
16-bit
Address
12 Row
For 8-bit SDRAM, PGSZ = 00 (256 words)
9 column address = 512 memory space
64Mbit SDRAM
Address
9 Column
8-bit