CY28411 Cypress Semiconductor, CY28411 Datasheet - Page 2

• Manufacturer Part Number: CY28411
• Description: Clock Generator for Intel Alviso Chipset
• Manufacturer: Cypress Semiconductor

Document #: 38-07594 Rev. *B
Pin Definitions
54
44,43,41,40
36,35
14,15
12
16
53
39
56,3,4,5
55
8
9
52
46
47
26,27
24,25,22,23,
19,20,17,18,
33,32,31,30
11
42
1,7
48
21,28,34
37
13
45
2,6
51
29
38
10
50
49
Pin No.
CPUT2_ITP/SRCT7,
PCI
PCI_STP#
SCLK
SRC4_SATAT,
VDD_CPU
VDD_PCI
VDD_REF
VDD_SRC
VDDA
CPU_STP#
CPUT/C
CPUC2_ITP/SRCC7
DOT96T, DOT96C
FS_A/USB_48
FS_B/TEST_MODE
FS_C/TEST_SEL
IREF
PCIF0/ITP_EN
PCIF1
REF
SDATA
SRC4_SATAC
SRCT/C
VDD_48
VSS_48
VSS_CPU
VSS_PCI
VSS_REF
VSS_SRC
VSSA
VTT_PWRGD#/PD
XIN
XOUT
Name
I/O, SE 3.3V-tolerant input for CPU frequency selection/fixed 48-MHz clock output.
I/O, SE 33-MHz clock/CPU2 select (sampled on the VTT_PWRGD# assertion).
O, DIF Differential CPU clock outputs.
O, DIF Selectable differential CPU or SRC clock output.
O, DIF Fixed 96-MHz clock output.
O, DIF Differential serial reference clock. Recommended output for SATA.
O, DIF Differential serial reference clocks.
O, SE 33-MHz clocks.
O, SE 33-MHz clocks.
O, SE Reference clock. 3.3V 14.318-MHz clock output.
O, SE 14.318-MHz crystal output.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for PLL.
GND
I, PU
I, PU
I, PU
GND
GND
GND
GND
GND
Type
I/O
I
I
I
I
I
3.3V LVTTL input for CPU_STP# active low.
ITP_EN = 0 @ VTT_PWRGD# assertion = SRC7
ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Hi-Z when
in test mode
0 = Hi-Z, 1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
3.3V-tolerant input for CPU frequency selection. Selects test mode if pulled
to V
Refer to DC Electrical Specifications table for V
cations.
A precision resistor is attached to this pin, which is connected to the internal
current reference.
3.3V LVTTL input for PCI_STP# active low.
1 = CPU2_ITP, 0 = SRC7
SMBus-compatible SCLOCK.
SMBus-compatible SDATA.
Ground for outputs.
Ground for outputs.
Ground for outputs.
Ground for outputs.
Ground for outputs.
Ground for PLL.
3.3V LVTTL input is a level sensitive strobe used to latch the USB_48/FS_A,
FS_B, FS_C/TEST_SEL and PCIF0/ITP_EN inputs. After VTT_PWRGD#
(active low) assertion, this pin becomes a real-time input for asserting power
down (active high).
14.318-MHz crystal input.
IMFS_C
when VTT_PWRGD# is asserted low.
Description
ILFS_C
,V
IMFS_C
,V
CY28411
IHFS_C
Page 2 of 19
specifi-