CY2DP1510 Cypress Semiconductor, CY2DP1510 Datasheet

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CY2DP1510

Manufacturer Part Number
CY2DP1510
Description
1:10 LVPECL Fanout Buffer
Manufacturer
Cypress Semiconductor
Datasheet

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Part Number:
CY2DP1510AXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Part Number:
CY2DP1510AXI
Manufacturer:
Cypress Semiconductor Corp
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CY2DP1510AXI
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Features
Logic Block Diagram
Cypress Semiconductor Corporation
Document Number: 001-55566 Rev. *G
Note
1. Input AC-coupling capacitors are required for voltage-translation applications.
Select one of two low-voltage positive emitter-coupled logic
(LVPECL) input pairs to distribute to 10 LVPECL output pairs
40-ps maximum output-to-output skew
600-ps maximum propagation delay
0.11-ps maximum additive RMS phase jitter at 156.25 MHz
(12-kHz to 20-MHz offset)
Up to 1.5-GHz operation
32-Pin thin quad flat pack (TQFP) package
2.5-V or 3.3-V operating voltage
Commercial and industrial operating temperature range
IN_SEL
IN0
IN0#
IN1
IN1#
V
V
V
SS
BB
DD
[1]
198 Champion Court
1:10 LVPECL Fanout Buffer with Selectable
100k
Functional Description
The
low-propagation delay 1:10 LVPECL fanout buffer targeted to
meet the requirements of high-speed clock distribution
applications. The CY2DP1510 can select between two separate
LVPECL input clock pairs using the IN_SEL pin. The device has
a fully differential internal architecture that is optimized to
achieve low additive jitter and low skew at operating frequencies
of up to 1.5 GHz.
CY2DP1510
San Jose
,
is
CA 95134-1709
V
DD
an
ultra-low
Q0
Q0#
Q1
Q1#
Q2
Q2#
Q3
Q3#
Q4
Q4#
Q5
Q5#
Q6
Q6#
Revised February 25, 2011
Q7
Q7#
Q8
Q8#
Q9
Q9#
Clock Input
noise,
CY2DP1510
408-943-2600
low
skew,
[+] Feedback

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CY2DP1510 Summary of contents

Page 1

... CY2DP1510 low-propagation delay 1:10 LVPECL fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The CY2DP1510 can select between two separate LVPECL input clock pairs using the IN_SEL pin. The device has a fully differential internal architecture that is optimized to achieve low additive jitter and low skew at operating frequencies ...

Page 2

... Operating Conditions....................................................... 4 DC Electrical Specifications ............................................ 5 AC Electrical Specifications ............................................ 6 Ordering Information........................................................ 9 Ordering Code Definition............................................. 9 Package Dimension......................................................... 10 Acronyms ........................................................................ 11 Document Number: 001-55566 Rev. *G Document Conventions ................................................. 11 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 13 Worldwide Sales and Design Support....................... 13 Products .................................................................... 13 PSoC Solutions ......................................................... 13 CY2DP1510 Page [+] Feedback ...

Page 3

... LVPECL reference voltage output LVPECL input clock. Active when IN_SEL = High LVPECL complementary input clock. Active when IN_SEL = High Ground LVPECL complementary output clocks LVPECL output clocks Exposed paddle. Connect to ground plane for package heat dissipation. No electrical connection. CY2DP1510 Q7# ...

Page 4

... Document Number: 001-55566 Rev. *G Condition Nonfunctional Nonfunctional SS Nonfunctional SS Nonfunctional JEDEC STD 22-A114-B At 1/8 in Condition 2.5-V supply 3.3-V supply Commercial Industrial Power-up time for V DD minimum specified voltage (power ramp must be monotonic). CY2DP1510 Min Max Unit –0.5 4.6 V –0.5 lesser of 4 0.4 DD –0.5 lesser of 4 0.4 DD – ...

Page 5

... DD [4] Input = V SS Terminated with 50 Ω [5] – 2.0 DD Terminated with 50 Ω [5] – 2 150 μA output current IN_SEL pin Measured at 10 MHz; per pin minimum of greater than 200 mV. ID CY2DP1510 Min Max Unit – 120 mA – 0 –0.3 – 0.3 ...

Page 6

... MHz, 12 kHz to 20 MHz – offset; input rise/fall time < 150 ps (20% to 80%), V > ID 400 mV 50% duty cycle at input, – 20% to 80% of full swing ( Input rise/fall time < 1.5 ns (20% to 80%) CY2DP1510 Typ Max Unit – 1.5 GHz – 1.5 GHz – – mV – – mV – ...

Page 7

... Figure 4. Input to Any Output Pair Propagation Delay Document Number: 001-55566 Rev Figure 3. Output Differential Voltage Figure 5. Output Duty Cycle PERIOD ODC t PERIOD CY2DP1510 )/2 ICM Page [+] Feedback ...

Page 8

... Document Number: 001-55566 Rev SK1 t SK1 D Figure 7. RMS Phase Jitter Phase noise Offset Frequency f2 f1 RMS Jitter ∝ Area Under the Masked Phase Noise Plot Figure 8. Output Rise/Fall Time 80% 80% 20 CY2DP1510 Phase noise mark V PP Page [+] Feedback ...

Page 9

... Temperature range C = Commercial I = Industrial Pb-free TQFP package Number of differential output pairs Base part number Company ID Cypress CY2DP1510 Production Flow Commercial, 0 ° °C Commercial, 0 ° °C Industrial, –40 ° °C Industrial, –40 ° °C Page [+] Feedback ...

Page 10

... Package Dimension Figure 9. 32-Pin Thin Plastic Quad Flat Pack 7 × 7 × 1.0 mm Document Number: 001-55566 Rev. *G CY2DP1510 001-54497 *A Page [+] Feedback ...

Page 11

... Unit of Measure °C degree Celsius dBc decibels relative to the carrier GHz giga hertz Hz hertz KΩ kilo ohm µA microamperes µF micro Farad µs microsecond mA milliamperes ms millisecond mV millivolt MHz megahertz ns nanosecond Ω ohm pF pico Farad ps pico second V volts W watts CY2DP1510 Page [+] Feedback ...

Page 12

... Document History Page Document Title: CY2DP1510 1:10 LVPECL Fanout Buffer with Selectable Clock Input Document Number: 001-55566 Orig. of Submission Revision ECN Change ** 2782891 CXQ *A 2838916 CXQ *B 2885033 CXQ *C 3011766 CXQ *D 3017258 CXQ *E 3100234 CXQ *F 3135201 CXQ *G 3090938 CXQ Document Number: 001-55566 Rev. *G ...

Page 13

... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-55566 Rev. *G All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised February 25, 2011 CY2DP1510 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 ...

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