AN2405 Freescale Semiconductor / Motorola, AN2405 Datasheet
AN2405
Related parts for AN2405
AN2405 Summary of contents
Page 1
... ARM® core based system. © Freescale Semiconductor, Inc., 2004. All rights reserved. Rev. 1.1, 11/2004 Contents Features and Supported Panels . . . . . . . . . . . . 1 LCDC Pins and Signals . . . . . . . . . . . . . . . . . . . 2 LCD Interface Clock Settings Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Interfacing to Sharp TFT Panels . . . . . . . . . . . . 9 Other Considerations . . . . . . . . . . . . . . . . . . . 11 Revision History . . . . . . . . . . . . . . . . . . . . . . . . 18 AN2405/D ...
Page 2
LCDC Pins and Signals Panel Panel Type BPP Interface Number of Levels (bits) Mono 1 1,2,4,8 2 level black and white chrome 2 1,2,4,8 4 gray scale levels 4 1,2,4,8 16 gray scale levels CSTN color levels ...
Page 3
LCD Interface Clock Settings The frequency setting of the interface clock, LSCLK, is determined by the panel specifications. To avoid flicker on the screen set LSCLK to be within the panel specifications. Use an oscilloscope to probe LSCLK to ...
Page 4
LCD Interface Clock Settings Figure 2 shows that the LCD controller’s clock input is PERCLK2. PERCLK2, with respect to the LCDC, is known as LCDC_CLK. Therefore, LCDC_CLK and HCLK are derived from the same clock source, the output of the ...
Page 5
Timing The LCDC supports both non-TFT passive matrix panels as well as TFT active matrix panels. Timing for both panel types are discussed in this section. Figure 3 and Table 1 depict the LSCLK-to-display data (LD) relationship. LSCLK LD[15:0] ...
Page 6
Timing Symbol Parameter T1 HSYNC to VSYNC delay T2 HSYNC pulse width T3 VSYNC to SCLK T4 SCLK to HSYN • VSYNC, HSYNC, and LSCLK can be programmed as active high or active low. In the timing diagram above, all ...
Page 7
TFT Timing for Display Region VSYNC C C HSYNC L LOE LD[15:0] C HSYNC LSCLK L LOE LD[15:0] Figure 5. TFT Panel Timing Waveform for Display Region Table 4. TFT Panel Timing for Display Region Symbol Parameter T1 Idle ...
Page 8
Timing Table 4. TFT Panel Timing for Display Region (continued) Symbol Parameter T8 Dummy idle state (Sharp = the LSCLK period which equals LCDC_CLK / (PCD + 1). • VSYNC, HSYNC and LOE can be programmed as ...
Page 9
Interfacing to Sharp TFT Panels The i.MX processor’s LCDC can directly interface with Sharp HR-TFT panels that require Sharp dedicated signals. Figure 7 shows how to connect the LCDC interface signals bpp TFT panel. The two ...
Page 10
Interfacing to Sharp TFT Panels Signal Name SPL/SPR 1 CLS PS 1 REV 1 Both the rising and falling edge of CLS and transition edge of REV are programmable. 5.2 Sharp Dedicated Signal Timing LSCLK R0-R5 G0-G5 D320 B0-B5 SPL ...
Page 11
Other Considerations 6.1 LCDC DMA Setting For SDRAM access, a fixed burst length preferred. For a heavily loaded bus and SDRAM access, a dynamic burst length is recommended. 6.2 Bandwidth and Detection of LCDC Under-Run The ...
Page 12
Other Considerations When an Under-Run occurs, the data output will be incorrect. When normal data service—that is, no more Under-Run, is restored the LCDC outputs data correctly. However, the LCD panel is a sequential device with no error checking protocol. ...
Page 13
Example Initializations Code Example 1. Sharp TFT VGA Panel Not Requiring Dedicated Signals comment ### Select CLKO mux to output HCLK(BCLK) ### setmem 0x21B000 0x2F00AC03, 32 comment ### Change BCLK (CPUCLK) to 16MHz comment setmem 0x21B000 0x2F009403, 32 comment ...
Page 14
Other Considerations comment vpwC480(dec) for 8bpp comment set vpw to 640/2=320 => 0x140 setmem 0x00205008 0x00000140, 32 comment set cursor position & attributes setmem 0x0020500C 0x40010001, 32 setmem 0x00205010 0x1F1F0000, 32 setmem 0x00205014 0x0000F800, 32 comment 16 bpp , tft ...
Page 15
Code Example 2 provides a way to configure the internal clocks of the i.MX chip, however depending on the application and system requirements the clocks could be different. i.MX Supplemental Information for LCD Interfacing Application Note, Rev. 1.1 Freescale Semiconductor ...
Page 16
Other Considerations Code Example 2. Sharp 320x480 TFT Requiring Dedicated Signals comment ### Select CLKO mux to output HCLK(BCLK) ### setmem 0x21B000 0x2F00AC03, 32 comment ### Change BCLK (CPUCLK) to 16MHz comment setmem 0x21B000 0x2F009403, 32 comment ### Change BCLK ...
Page 17
LLP active high, LFLM active low setmem 0x00205018 0xF8040042, 32 comment Sharp Configuration 1 Register setmem 0x00205028 0x00090300, 32 comment hsyn width = 2 CLK setmem ...
Page 18
Revision History 7 Revision History The changes from Revision 1 to revision 1.1 of this document follows: • Updated URL from Motorola to Freescale Semiconductor. i.MX Supplemental Information for LCD Interfacing Application Note, Rev. 1.1 18 Freescale Semiconductor ...
Page 19
Supplemental Information for LCD Interfacing Application Note, Rev. 1.1 Freescale Semiconductor NOTES 19 ...
Page 20
... Tai Po Industrial Estate Tai Po, N.T., Hong Kong 852-26668334 Home Page: www.freescale.com AN2405/D Rev. 1.1 11/2004 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...