AN2645 Freescale Semiconductor / Motorola, AN2645 Datasheet - Page 4

• Manufacturer Part Number: AN2645
• Description: Interfacing the Philips ISP1362 USB OTG Controller to the MCF5249
• Manufacturer: Freescale Semiconductor / Motorola

Hardware Design
2
The MCF5249 USB OTG reference design is developed around the M5249C3 evaluation board using a
daughter card for the USB OTG controller. The daughter card connects to the evaluation board using
expansion connectors already provided on the M5249C3 board.
The M5249C3 board provides an RS232 interface, BDM interface, 8 Mbyte SDRAM, and 2 Mbyte Flash
ROM for system development. For additional information on the evaluation board, including full
schematics, refer to the M5249C3 user’s manual on the MCF5249 web page.
The main features and key issues (interface, clocking, over-current protection, etc.) are explained in the
subsections below.
2.1
The ISP1362 is interfaced to the MCF5249 via the external bus interface. The external bus interface pins
are utilized as follows:
The USB controller supports programmed I/O (PIO) and Direct Memory Access (DMA); however, in this
design only PIO has been implemented.
PIO mode allows the MCF5249 to access the internal control registers and buffer memory of the ISP1362.
It occupies only four memory locations of the MCF5249. For recommended ISP1362 memory allocation,
refer to the ISP12362 data sheet:
2.2
The ISP1362 runs with a 12 MHz crystal with an on-chip PLL. The MCF5249 runs at 140 MHz with an
external bus speed of 70 MHz.
Please refer to the timing diagrams in the MCF5249 user manual and the ISP1362 data sheet.
The ISP1362 operates asynchronously. All data transmission is clocked on CS1 and/or OE and R/W.
Minimum times for read and write cycles in the ISP1362 are given as 25 ns and 22 ns respectively. In order
to maintain these timings, it is advised to add at least 1 wait state to CS1 on the MCF5249.
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A0 determines whether the controller is to be in the command or data phase.
A1 determines, on a per-access basis, whether the controller is to operate in host or device mode:
CS1 enables the HC/DC driver to access the buffer memory and registers of the HC/DC.
RD, when asserted low, indicates that the HC/DC driver is requesting a read to the buffer memory
and registers of the HC/DC.
WR, when asserted low, indicates that the HC/DC driver is requesting a write to the buffer
memory and registers of the HC/DC.
D[31:16] connects the external 16-bit data bus to the internal registers and buffer memory of the
ISP1362.
Hardware Design
MCF5249 External Bus Interface
Clocking
0
1
Host control (HC) is selected
Device control (DC) is selected
Interfacing the Philips ISP1362 USB OTG to the MCF5249
Freescale Semiconductor, Inc.
For More Information On This Product,
http://www.semiconductors.philips.com/buses/usb/products/otg/isp136x/
Go to: www.freescale.com
MOTOROLA