EM638165 Etron Technology Inc., EM638165 Datasheet

Page 1

... Interface: LVTTL 54-pin 400 mil plastic TSOP II package Overview The EM638165 SDRAM is a high-speed CMOS synchronous DRAM containing 64 Mbits internally configured as 4 Banks of 1M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented ...

Page 2

... ADDRESS BUFFER A11 BA0 BA1 REFRESH Preliminary CONTROL SIGNAL REGISTER 2 EM638165 1MX16 CELL ARRAY (BANK #A) Column Decoder DQ0 Buffer | DQ15 1MX16 CELL ARRAY (BANK #B) Column Decoder 1MX16 CELL ARRAY (BANK #C) ...

Page 3

... RAS# and WE# signals and is latched at the positive edges of CLK. When RAS# is held "HIGH" and CS# is asserted "LOW," the column access is started by asserting CAS# "LOW." Then, the Read or Write command is selected by asserting WE# "LOW" or "HIGH." Preliminary Table 1. Pin Details of EM638165 Description BA1 BA0 0 ...

Page 4

... No Connect: These pins should be left unconnected. V Supply DQ Power: Provide isolated power to DQs for improved noise immunity. DDQ ( 3.3V 0. Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. SSQ ( Supply Power Supply: +3. Supply Ground SS Preliminary 0.3V 4 EM638165 Rev 0.6 Feb. 2001 ...

Page 5

... L X Idle (SelfRefresh) Active (5) Any Active Any (PowerDown) Active Active EM638165 A A CS# RAS# CAS# WE# 0,1 10 0-9,11 V Row address Column L H address ( Column ...

Page 6

... AutoPrecharge t RAS# Cycle time ( ) RC AutoPrecharge (Burst Length = n, CAS# Latency = 3) (max.). Therefore, the precharge function must be performed RAS (max.). At the end of precharge, the precharged bank is still in the idle RAS 6 EM638165 Tn+3 Tn+4 Tn+5 Bank B Row Addr. Row Addr. t RAS# - RAS# delay time ( ) RRD Bank B NOP ...

Page 7

... DOUT B 0 DOUT B 1 DOUT A 0 DOUT B 0 (Burst Length = 4, CAS# Latency = NOP NOP NOP DOUT A 0 Must be Hi-Z before the Write Command (Burst Length 7 EM638165 NOP NOP NOP DOUT NOP NOP NOP DOUT B 2 DOUT B 3 DOUT B 1 ...

Page 8

... NOP (Burst Length Bank(s) NOP NOP Precharge DOUT A 0 DOUT A 2 DOUT A 1 DOUT A 0 DOUT A 1 Read to Precharge (CAS# Latency = EM638165 WRITE A NOP NOP DIN A 0 DIN A 1 DIN CAS# Latency = WRITE B NOP NOP ...

Page 9

... Input data must be removed from the DQ's at least one clock cycle before the Read data appears on the outputs to avoid data contention. (Burst Length = 4, CAS# Latency = EM638165 (min.) before the Write command NOP NOP ...

Page 10

... Write to Precharge + t (min.)}. At full-page burst, only the write operation Write A NOP NOP AutoPrecharge DIN A 0 DIN A 1 DIN A 0 DIN A 1 (Burst Length = 2, CAS# Latency = EM638165 NOP Activate NOP ROW NOP NOP NOP t DAL * t DAL ...

Page 11

... RP Mode Register PrechargeAll Any Set Command Command (CAS# Latency = WBL Test Mode CAS Latency A0 Burst Length Reserved 1 Reserved 0 Reserved 1 Full Page 11 EM638165 Burst Length Rev 0.6 Feb. 2001 T10 A0 ...

Page 12

... A1 A1 A2 A2# A1 A2# A1# A0 CAS# Latency 0 Reserved 1 Reserved 0 2 clocks 1 3 clocks X Reserved 12 EM638165 255 256 n+6 n+7 - n+255 n Burst Length 4 words Rev 0.6 257 - n words Feb. 2001 ...

Page 13

... T3 T4 NOP NOP Burst Stop DIN A 1 DIN A 2 don't care Input data for the Write is masked. (Burst Length = X, CAS# Latency = EM638165 NOP NOP NOP NOP The burst ends after a delay equal to the CAS# latency. DOUT A 3 DOUT A 2 ...

Page 14

... Preliminary (min.). To provide the AutoRefresh command, all banks need to RC (min), must be met before successive auto refresh operations are RP (min.) because time is required for the RC 14 EM638165 Rev 0.6 Feb. 2001 ...

Page 15

... I C Input/Output Capacitance I/O Note: These parameters are periodically sampled and are not 100% tested. Preliminary Item Rating - 1.0 ~ 4.6 -1 125 Min. Typ. 3.0 3.3 3.0 3.3 ¡ Ð 2.0 ¡ Ð - 0.3 Min EM638165 Unit Note °C °C 255 ° Max. Unit Note 3.6 V 3.6 V 4.6 V 0.8 V Max ...

Page 16

... IH I DD2P I DD2PS I DD3N = 15ns CK I DD3NS = CK I DD4 I DD5 I DD6 Description OUT DDQ ( I = -2mA ) OUT ( I = 2mA ) OUT 16 EM638165 = 3.3V 0.3V 0~70°C) - 6/7/7.5/8/10 Max. Unit 100 130 1 Min. Max. Unit Note - ¡ Ð 2.4 ¡ Ð 0.4 Rev 0.6 Note 3 3 ...

Page 17

... These parameters depend on the output loading. Specified values are obtained with the output open. 5. Power-up sequence is described in Note 11. Preliminary - Min. 60/63/68/70/80 18/20/20/20/24 18/20/20/20/24 12/14/15/20/25 42/45/45/48/ CL /10/10/13 CL 6/7/7.5/8/10 2/2.5/2.5/3/3 2/2.5/2.5/3 2.5/2.7/3/3/3 1 1/1.5/1.3/2/2.5 1/0.8/0.8/0.8/0.8 6/7/7.5/8/ Input signals are changed one time during t 17 EM638165 6/7/7.5/8/10 Max. Unit ns CLK - / - /6/6/7 5/5.4/5.4/6/7 ns 5/5.4/5.4/6 Rev 0.6 Note Feb. 2001 ...

Page 18

... LVTTL A.C. Test Load (B) and V . Transition(rise and fall) of input signals are -0.5) ns should be added to the parameter & and V (simultaneously) when all input signals are held "NOP" state DD DDQ 18 EM638165 1.4V / 1.4V 2.4V / 0.4V 1ns 1.4V 1. 30pF Rev 0.6 Feb. 2001 ...

Page 19

... RC Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Activate Write with Activate Write Command AutoPrecharge Command Command Bank B Command Bank A Bank A Bank B 19 EM638165 t IS RAz RBy RAz RBy RRD t IH Ay1 Ay2 Ay3 Precharge Activate Activate Command Command ...

Page 20

... RAS AC2 t AC2 HZ t RCD t LZ Ax0 Ax1 t OH Read Activate Command Command Auto Precharge Bank A Bank B 20 EM638165 T8 T9 T10 T 11 T12 Begin AutoPrecharge Bank RAy CBx RAy Bx0 Bx1 t HZ Read with Precharge Activate Command Command ...

Page 21

... Preliminary (Burst Length=4, CAS# Latency= T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 AutoRefresh Command 21 EM638165 RAx RAx CAx Ax0 Ax1 Ax2 Ax3 Read Activate Command Command Bank A Bank A Rev 0.6 Feb. 2001 ...

Page 22

... Inputs must be Set Command stable for 200 s Preliminary T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Minimum of 2 Refresh Cycles are required 2nd Auto Refresh Command Command 22 EM638165 t RC Any Command Rev 0.6 Feb. 2001 ...

Page 23

... Preliminary T10 T11 T6 *Note 4 *Note 3 t SRX *Note 5 *Note 6 Hi-Z SelfRefresh Exit is required before exit from SelfRefresh. RAS SRX 23 EM638165 T12 T13 T14 T15 T16 T17 T18 t RC(min) *Note 7 t PDE *Note 8 AutoRefresh . Rev 0.6 Feb. 2001 T19 ...

Page 24

... Clock Suspend Command Bank A Read Command Bank A Note: CKE to CLK disable/enable = 1 clock Preliminary T10 T13 T14 T15 T16 T17 T1 T19 T20 T21 T22 Ax3 Ax1 Ax2 Clock Suspend Clock Suspend 1 Cycle 2 Cycles 3 Cycl EM638165 Rev 0.6 Feb. 2001 ...

Page 25

... Bank A Note: CKE to CLK disable/enable = 1 clock Preliminary T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Ax3 Ax0 Ax1 Ax2 Clock Suspend Clock Suspend Clock Suspend 2 Cycles 1 Cycle 3 Cycl EM638165 t HZ Rev 0.6 Feb. 2001 ...

Page 26

... Bank A Bank A Note: CKE to CLK disable/enable = 1 clock Preliminary T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 Ax0 Ax1 Ax2 Clock Suspend Clock Suspend 1 Cycle 2 Cycles 26 EM638165 t HZ Ax3 Clock Suspend 3 Cycles Rev 0.6 Feb. 2001 ...

Page 27

... Clock Suspend Command 1 Cycle Bank A Write Command Bank A Note: CKE to CLK disable/enable = 1 clock Preliminary T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 DAx1 DAx2 DAx3 Clock Suspend Clock Suspend 2 Cycles 3 Cycles 27 EM638165 Rev 0.6 Feb. 2001 ...

Page 28

... Clock Suspend Command 1 Cycle Bank A Write Command Bank A Note: CKE to CLK disable/enable = 1 clock Preliminary T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 DAx2 DAx3 DAx1 Clock Suspend Clock Suspend 2 Cycles 3 Cycles 28 EM638165 T2 2 Rev 0.6 Feb. 2001 ...

Page 29

... Clock Suspend Command Bank A Write Command Bank A Note: CKE to CLK disable/enable = 1 clock Preliminary T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 DAx2 DAx3 DAx1 Clock Suspend Clock Suspend 1 Cycle 2 Cycles 3 Cycles 29 EM638165 Rev 0.6 Feb. 2001 ...

Page 30

... T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CAx Ax0 Ax1 Ax2 Read Clock Mask Clock Mask Command Start End Bank A 30 EM638165 t PDE Valid t HZ Ax3 PRECHARGE STANDBY Precharge Power Down Command Mode Exit Bank A ...

Page 31

... T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 RAz CAy RAz CAx Aw3Ax0 Ax1 Ay1 Ay2 Ay3 Ay0 Read Read Precharge Command Command Command Bank A Bank A Bank A Activate Command Bank A 31 EM638165 CAz Az1 Az2 Az3 Az0 Read Command Bank A Rev 0.6 Feb. 2001 ...

Page 32

... T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CAx CAy Ax1 Ay0 Aw0 Aw1 Aw2 Aw3 Ax0 Ay1 Read Read Precharge Command Command Command Bank A Bank A Bank A 32 EM638165 RAz RAz CAz Az0 Ay2 Ay3 Az1 Activate Read Command Command Bank A Bank A Rev 0.6 Feb. 2001 Az2 ...

Page 33

... T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CAy CAx Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Read Read Command Command Bank A Bank A 33 EM638165 RAz CAz RAz Ay1 Ay2 Ay3 Precharge Activate Read Command Command Command Bank A ...

Page 34

... T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CBy CBx DBx1 DBy0 DBy1 DBy2 DBy3 DBw3 DBx0 Write Precharge Write Command Command Command Bank B Bank B Bank A Command 34 EM638165 RBz RBz CBz DBz0 DBz1 DBz2 DBz3 Write Command Bank B Activate Bank B Rev 0.6 Feb. 2001 ...

Page 35

... T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CBy CBx DBy2 DBy3 Write Write Precharge Command Command Command Bank B Bank B Bank B 35 EM638165 RBz RBz CBz DBz0 DBz1 DBz2 DBz3 Activate Write Command Command Bank B Bank B Rev 0.6 Feb. 2001 ...

Page 36

... T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CBx CBy Write Write Command Command Bank B Bank B 36 EM638165 RBz RBz CBz DBz0 DBz1 Precharge Activate Write Command Command Command Bank B Bank B Bank B Rev 0.6 Feb. 2001 ...

Page 37

... RP Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Activate Precharge Command Command Bank A Bank B Activate Read Command Command Bank B Bank A 37 EM638165 CBy By0 By1 Ax4 Ax5 Ax6 Ax7 Read Precharge Command Command Bank B Bank A Rev 0.6 Feb. 2001 By2 ...

Page 38

... RP Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Activate Precharge Command Command Command Bank A Bank B Read Command Bank A 38 EM638165 RBy RBy CBy Ax1 Ax2 Ax3 Ax6 Ax7 Ax4 Ax5 Activate Read Command Bank B Bank B Rev 0.6 By0 By1 Feb. 2001 ...

Page 39

... T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 RAx RAx CAx AC3 Bx6 Bx7 Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Activate Read Command Command Bank A Bank A 39 EM638165 RBy RBy CBy t RP Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Precharge Activate Read Precharge Command Command ...

Page 40

... T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 RBx RBx CBx DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 Activate Precharge Command Command Bank B Write Command Bank B 40 EM638165 RAy RAy CAy DBx7 DAy0 DAy1 DAy2 Precharge Write Command Command Bank A ...

Page 41

... WR* RP DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 Activate Write Activate Command Command Command Bank B Bank B Bank A Precharge Command Bank A 41 EM638165 CAy t WR* DBx7 DAy3 DAy0 DAy1DAy2 DAy4 Write Command Bank A Precharge Command Bank B Rev 0.6 Feb. 2001 ...

Page 42

... T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 RBx CBx RBx t WR* DAx6 DAx7 DBx0 DBx1 DBx2 Activate Write Precharge Command Command Command Bank B Bank B Bank A 42 EM638165 RAy RAy CAy WR* DAy0 DAy1 DAy2 DBx3 DBx4 DBx5 DBx6 DBx7 Write Activate Precharge Command Command Command ...

Page 43

... T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CAy Ax2 Ax3 DAy0DAy1 The Write Data Write is Masked with a Command Bank A Zero Clock Latency 43 EM638165 CAz Az3 DAy3 Az0 Az1 Read The Read Data Precharge Command is Masked with a Command Bank A ...

Page 44

... T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CAy Ax0 Ax1 Ax2 Ax3 DAy0 DAy1 Write The Write Data Command is Masked with a Bank A Zero Clock Latency 44 EM638165 CAz DAy3 Az0 Az1 Read The Read Data Command is Masked with a Bank A Two Clock Latency Rev 0.6 Az3 Feb. 2001 ...

Page 45

... T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CAy Ax0 Ax1 Ax2 Ax3 DAy0 DAy1 Write The Write Data Command is Masked with a Bank A 45 EM638165 CAz DAy3 Az0 Az1 Read The Read Data Command is Masked with a Zero Clock Bank A Two Clock ...

Page 46

... Bw1 Bx0 Bx1 By0 By1 Ay0 Activate Read Read Read Command Command Command Command Bank B Read Bank B Bank B Bank A Command Bank B 46 EM638165 CBz Bz2 Bz3 Ay1 Bz0 Bz1 Read Precharge Precharge Command Command Command Bank B Bank A Bank B Rev 0.6 Feb. 2001 ...

Page 47

... Ax1 Ax2 Ax3 Bw0 Bw1 Bx0 Bx1 Activate Read Read Read Command Command Command Command Bank B Bank B Bank B Bank B 47 EM638165 CAy CBz Bz2 Bz3 By0 Ay1 Bz1 By1 Ay0 Bz0 Read Read Precharge Command Command Command Bank A Bank B Bank B Precharge ...

Page 48

... Bx0 Bx1 Ax0 Ax1 Ax2 Ax3 Read Read Read Command Command Command Bank B Bank B Bank B Activate Command Bank B 48 EM638165 CAy By0 By1 Bz1 Ay0 Ay2 Bz0 Ay1 Ay3 Precharge Read Prechaerge Command Command Command Bank A Bank A Bank B Rev 0.6 Feb. 2001 ...

Page 49

... CBx CAy CBw DBw0 DBw1 DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 Write Write Write Write Command Command Command Command Bank B Bank B Bank B Bank A 49 EM638165 CBz DBz2 DBz0 DBz1 DBz3 Write Precharge Command Command Bank B Bank B Precharge Command Bank A Rev 0 ...

Page 50

... CBw CBx CBy DBw0 DBw1 DBx0 DBx1 DBy0 DBy1DAy0 Activate Write Write Write Command Command Command Bank B Bank B Bank B Bank B 50 EM638165 CAy CBz DAy1 DBz0 DBz1 DBz2 DBz3 Write Write Precharge Command Command Command Bank A Bank B Bank B ...

Page 51

... T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 RBw CBw CBx CBy DBw0 DBw1DBx0 DBx1 DBy0 Activate Write Write Write Command Command Command Bank B Bank B Bank B Bank B 51 EM638165 CAy CBz WR(min) DBz1 DBz2 DBz3 DBy1 DAy0 DAy1 DBz0 Write Write Precharge Command Command Command Bank A ...

Page 52

... Bx0 Bx1 Bx2 Bx3 Ay1 Ay2 Activate Command Auto Precharge Bank B Read with Read with Auto Precharge Command Command Bank B Bank A 52 EM638165 RBz CBy RBz CBz Ay3 By0 By1 By3 By2 Bz0 Read with Activate Command Command Bank B Bank B Read with ...

Page 53

... Bx0 Bx1 Bx2 Bx3 Ay0 Read with Read with Activate Auto Precharge Auto Precharge Command Command Command Bank B Bank B Bank A 53 EM638165 RAz CAz CBy RAz Ay1 Ay2 Ay3 By0 By1 By2 By3 Az0 Read with Activate Read with Auto Precharge ...

Page 54

... Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Read with Auto Precharge Command Read with Bank B Auto Precharge Command Bank A 54 EM638165 RBy CBy RBy Ay0 Ay1 Ay2 Ay3 By0 By1 By2 Activate Read with Command Auto Precharge Bank B Command Bank B Rev 0 ...

Page 55

... DAy0 DAy3 DBy0 DBx0 DBx1 DBx2 DBx3 DAy1DAy2 Activate Command Auto Precharge Bank B Bank B Write with Auto Precharge Command Bank A 55 EM638165 RAz RAz CAz CBy DBy1 DBy2 DBy3 DAz0 DAz0 Activate Write with Command Bank A Command Bank B Write with Auto Precharge ...

Page 56

... DBx0 DBx1 DBx2 DBx3 DAy1 DAy2 Write with Write with Activate Auto Precharge Auto Precharge Command Command Command Bank B Bank B Bank A 56 EM638165 RAz RBy CAz CBy RAz DBy1 DBy2 DBy3 DAz2 DAz3 DBy0 DAz0 DAz1 Write with Activate Write with Auto Precharge ...

Page 57

... T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CBx CAy DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 Write with Write with Auto Precharge Auto Precharge Command Command Bank B Bank A 57 EM638165 ` RBy RBy CBy DBy1 DBy2DBy3 DAy3 DBy0 Activate Write with Command Auto Precharge Bank B Command Bank B Rev 0 ...

Page 58

... Bx+1 Ax-2 Ax-1 Ax Ax+1 Bx Bx+2 Bx+3 Bx+4 Read Command Bank B Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning the starting address. 58 EM638165 RBy RBy t RP Bx+6 Bx+7 Bx+5 Precharge Command Bank B Burst Stop Activate Command Command Bank B Rev 0 ...

Page 59

... Command terminate when the burst length is satisfied; Bank B The burst counter wraps the burst counter increments and continues from the highest order bursting beginning the starting address. page address back to zero during this time interval 59 EM638165 RBy RBy t RP Bx+2 Bx+3 Bx+4 Bx+5 Bx+6 Precharge ...

Page 60

... Bank B Bank B satisfied; the burst counter The burst counter wraps increments and continues from the highest order bursting beginning with the page address back to zero starting address. during this time interval 60 EM638165 RBy RBy t RP Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Precharge Activate Command ...

Page 61

... DAx Write Command Bank B Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. 61 EM638165 RBy RBy Data is ignored Precharge Command Bank B Burst Stop Activate Command Command Bank B Rev 0 ...

Page 62

... DBx+ 4 DBx+ 5 DBx+ 6 Write Command Bank B Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. 62 EM638165 RBy RBy Data is ignored Precharge Activate Command Command Bank B Bank B ...

Page 63

... EM638165 RBy RBy Data is ignored DBx+ 4 DBx+ 5 Precharge Activate Command ...

Page 64

... CAz DAy1 DAy2 Ax1 Ax2 Ax1 Ax2 Ax3 DAy0 DAy1 DAy3 Write Lower Byte Upper 3 Bytes Read Command is masked are masked Command Bank A Bank A 64 EM638165 Az1 Az2 Az1 Az2 Az3 Az0 Lower Byte Lower Byte is masked is masked Rev 0.6 Feb. 2001 ...

Page 65

... Read Read Read Read Bank B Bank A Bank B Bank A with Auto with Auto with Auto with Auto Precharge Precharge Precharge Precharge 65 EM638165 Begin Auto Begin Auto Begin Auto Begin Auto Precharge Precharge Precharge Precharge Bank A Bank B Bank A Bank B RAx RBz RBy RAy ...

Page 66

... CBy Ax0 Bx0 Ay0 Ay1 By0 By1 Az0 Az1 Read Read Read Command Command Bank B Bank B Bank A Read Command Bank A 66 EM638165 RBw CBz RBw t RP Az2 Bz0 Bz1 Bz2 Read Precharge Command Command Bank B Bank B (Precharge Temination) Activate Command Bank B Rev 0 ...

Page 67

... CBx CAy CBy CAz DAy1 DBy0 DBy1 DAz0 DAz1 DAz2 DBz0 DBz1 Write Write Write Command Command Bank B Bank B Bank A Write Command Bank A 67 EM638165 RBw CBz RBw DBz2 Write Precharge Command Command Bank B Bank B (Precharge Temination) Activate Command ...

Page 68

... CAy RAy Ay0 Ay1 Ay2 Read Precharge Precharge Command Command Command Bank A Bank A Activate Command Bank A 68 EM638165 RAz RAz CAz t RP Precharge Termination of a Read Burst. DAz0 DAz1 DAz2 DAz3 DAz4 DAz5 Write Command Bank A Bank A Activate Command Bank A Rev 0 ...

Page 69

... RAy RAy CAy Ay0 Ay1 Precharge Precharge Activate Read Command Command Command Command Bank A Bank A Bank A Bank A 69 EM638165 RAz RAz CAz Ay2 Az0 Az1 Az2 Precharge Activate Read Command Command Command Bank A Bank A Bank A Precharge Termination of a Read Burst Rev 0 ...

Page 70

... T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 RAy CAy RAy t RP Precharge Read Activate Command Command Command Bank A Bank A Bank A Precharge Termination of a Write Burst 70 EM638165 RAz RAz t RP Ay0 Ay1 Ay2 Precharge Activate Precharge Termination Command Command of a Read Burst Bank A Bank A Rev 0.6 Feb. 2001 ...

Page 71

... EM638165 Normal Max - 1.194 0.1 0.150 - 1.044 0.35 0.40 1.165 0.210 22.238 22.327 10.16 10.262 0.80 - 11.8365 11.938 0.50 0.597 0. Rev 0.6 Feb. 2001 L ...