EM6517 ETC, EM6517 Datasheet - Page 41

• Manufacturer Part Number: EM6517
• Description: 4 BIT MICROCONTROLLER
• Manufacturer: ETC

Figure 30. Ram Architecture
The main RAM (RAM1) is direct addressable on addresses decimal(0 to 63). A second RAM (RAM2) is indirect
addressable on addresses 64,65, 66 and 67 together with the index from RegIndexAdr.
The RAM2 addressing is indirect using the RegIndexAdr value as an offset to the directly addressed base
RAM2_0, RAM2_1 , RAM2_2 or RAM2_3 registers.
To write or read the RAM2 the user has first to set the offset value in the RegIndexAdr register. The actual
access then is made on the RAM2 base addresses RAM2_0 , RAM2_1, RAM2_2 or RAM2_3. Refer to
Figure 30. Ram Architecture, for the address mapping.
i.e. Writing hex(5) to Ram2 add location 30: First write hex(E) to RegIndexAdr, then write hex(5) to RAM2_1
RAM Extension : Unused R/W Registers can often be used as possible RAM extension. Be careful not to use
register which start, stop, or reset some functions.
RAM1_0
RAM1_63
RAM1_62
RAM1_61
RAM1_60
RAM1_3
RAM1_2
RAM1_1
64 x 4 direct addressable RAM1
.
.
.
FOR ENGINEERING ONLY
4 bit R/W
4 bit R/W
4 bit R/W
4 bit R/W
4 bit R/W
4 bit R/W
4 bit R/W
4 bit R/W
.
.
.
RAM2_0
RAM2_3
RAM2_2
RAM2_1
64 x 4 indexed addressable RAM2
RegIndexAdr[1]
RegIndexAdr[F]
RegIndexAdr[E]
RegIndexAdr[1]
RegIndexAdr[0]
RegIndexAdr[F]
RegIndexAdr[E]
RegIndexAdr[1]
RegIndexAdr[0]
RegIndexAdr[F]
RegIndexAdr[E]
RegIndexAdr[1]
RegIndexAdr[0]
RegIndexAdr[F]
RegIndexAdr[E]
RegIndexAdr[0]
...
...
...
...
© EM Microelectronic-Marin SA, 09/99, Rev. A/277
EM6517
4 bit R/W
4 bit R/W
4 bit R/W
4 bit R/W
4 bit R/W
4 bit R/W
4 bit R/W
4 bit R/W
4 bit R/W
4 bit R/W
4 bit R/W
4 bit R/W
4 bit R/W
4 bit R/W
4 bit R/W
4 bit R/W
...
...
...
...
41