IDT72261LA15PF IDT, Integrated Device Technology Inc, IDT72261LA15PF Datasheet - Page 14

• Manufacturer Part Number: IDT72261LA15PF
• Description: IC FIFO 8192X18 LP 15NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72261LA15PF

• Function: Synchronous
• Memory Size: 144K (8K x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72261LA15PF

valid on the outputs. OR stays LOW after the RCLK LOW to HIGH transition
that shifts the last word from the FIFO memory to the outputs. OR goes
HIGH only with a true read (RCLK with REN = LOW). The previous data
stays at the outputs, indicating the last word was read. Further data reads
are inhibited until OR goes LOW again. See Figure 10, Read Timing (FWFT
Mode), for the relevant timing information.
mode, OR is a triple register-buffered output.
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (MRS), PAF will go LOW after (D - m) words are
written to the FIFO. The PAF will go LOW after (16,384-m) writes for the
IDT72261LA and (32,768-m) writes for the IDT72271LA. The offset “m” is
the full offset value. The default setting for this value is stated in the footnote
of Table 1.
IDT72261LA and (32,769-m) writes for the IDT72271LA, where m is the full
offset value. The default setting for this value is stated in the footnote of
Table 2.
and FWFT Mode), for the relevant timing information.
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
reaches the almost-empty condition. In IDT Standard mode, PAE will go
IDT72261LA/72271LA SuperSync FIFO™
16,384 x 9 and 32,768 x 9
In IDT Standard mode, EF is a double register-buffered output. In FWFT
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
In FWFT mode, the PAF will go LOW after (16,385-m) writes for the
See Figure 16, Programmable Almost-Full Flag Timing (IDT Standard
PAF is synchronous and updated on the rising edge of WCLK.
The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO
EF/OR is synchronous and updated on the rising edge of RCLK.
14
LOW when there are n words or less in the FIFO. The offset “n” is the empty
offset value. The default setting for this value is stated in the footnote of
Table 1.
in the FIFO. The default setting for this value is stated in the footnote of Table
2.
and FWFT Mode), for the relevant timing information.
HALF-FULL FLAG (HF)
FIFO beyond half-full sets HF LOW. The flag remains LOW until the
difference between the write and read pointers becomes less than or equal
to half of the total depth of the device; the rising RCLK edge that accom-
plishes this condition sets HF HIGH.
PRS), HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 16,384
for the IDT72261LA and 32,768 for the IDT72271LA.
will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 16,385 for the
IDT72261LA and 32,769 for the IDT72271LA.
for the relevant timing information. Because HF is updated by both RCLK
and WCLK, it is considered asynchronous.
DATA OUTPUTS (Q
In FWFT mode, the PAE will go LOW when there are n+1 words or less
See Figure 17, Programmable Almost-Empty Flag Timing (IDT Standard
PAE is synchronous and updated on the rising edge of RCLK.
This output indicates a half-full FIFO. The rising WCLK edge that fills the
In IDT Standard mode, if no reads are performed after reset (MRS or
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
See Figure 18, Half-Full Flag Timing (IDT Standard and FWFT Modes),
(Q
0
- Q
8
) are data outputs for 9-bit wide data.
0
-Q
8
)
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
JANUARY 7, 2009