IDT72261LA15PF IDT, Integrated Device Technology Inc, IDT72261LA15PF Datasheet - Page 8

• Manufacturer Part Number: IDT72261LA15PF
• Description: IC FIFO 8192X18 LP 15NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72261LA15PF

• Function: Synchronous
• Memory Size: 144K (8K x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72261LA15PF

PROGRAMMING FLAG OFFSETS
IDT72261LA/72271LA has internal registers for these offsets. Default
settings are stated in the footnotes of Table 1 and Table 2. Offset values
can be programmed into the FIFO in one of two ways; serial or parallel
loading method. The selection of the loading method is done using the LD
(Load) pin. During Master Reset, the state of the LD input determines
whether serial or parallel flag offset programming is enabled. A HIGH on
LD during Master Reset selects serial loading of offset values and in
addition, sets a default PAE offset value of 3FFH (a threshold 1,023 words
from the empty boundary), and a default PAF offset value of 3FFH (a
threshold 1,023 words from the full boundary). A LOW on LD during Master
Reset selects parallel loading of offset values, and in addition, sets a
TABLE 1 — STATUS FLAGS FOR IDT STANDARD MODE
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
TABLE 2 — STATUS FLAGS FOR IDT STANDARD MODE
IDT72261LA/72271LA SuperSync FIFO™
16,384 x 9 and 32,768 x 9
Full and Empty Flag offset values are user programmable. The
Number of
Words in
FIFO
Number of
Words in
FIFO
(
1)
8,194 to (16,385-(m+1))
8,193 to (16,384-(m+1))
(16,384-m)
(16,385-m)
(n+2) to 8,193
(n+1) to 8,192
IDT72261LA
IDT72261LA
1 to n
16,385
16,384
1 to n+1
(2)
0
0
to 16,384
to 16,383
(1)
(1)
(2)
16,386 to (32,769-(m+1))
16,385 to (32,768-(m+1))
(32,768-m)
(32,769-m)
(n+2) to 16,385
8
(n+1) to 16,384
IDT72271LA
default PAE offset value of 07FH (a threshold 127 words from the empty
boundary), and a default PAF offset value of 07FH (a threshold 127 words
from the full boundary). See Figure 3, Offset Register Location and Default
Values.
the current offset values. It is only possible to read offset values via parallel
read.
rizes the control pins and sequence for both serial and parallel program-
ming modes. For a more detailed description, see discussion that follows.
after Master Reset, regardless of whether serial or parallel programming
has been selected.
IDT72271LA
1 to n+1
32,769
1 to n
In addition to loading offset values into the FIFO, it also possible to read
Figure 4, Programmable Flag Offset Programming Sequence, summa-
The offset registers may be programmed (and reprogrammed) any time
32,768
0
0
(2)
to 32,768
(1)
to 32,767
(1)
(2)
FF
IR
H
H
H
H
H
L
L
L
L
L
H
L
PAF HF
PAF HF
COMMERCIAL AND INDUSTRIAL
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
L
L
L
H
H
H
L
L
L
TEMPERATURE RANGES
PAE EF
PAE OR
H
H
H
H
L
L
H
H
H
H
L
L
4671 drw 05
JANUARY 7, 2009
H
H
H
H
H
H
L
L
L
L
L
L