IDT723626L15PF IDT, Integrated Device Technology Inc, IDT723626L15PF Datasheet - Page 10

• Manufacturer Part Number: IDT723626L15PF
• Description: IC FIFO SYNC 256X36X2 128QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT723626L15PF

• Function: Synchronous
• Memory Size: 18.4K (256 x 36 x 2)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 723626L15PF

NOTE:
1. Either a HIGH or LOW can be applied to a "don't care" input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily "don't care" (along with
SIGNAL DESCRIPTION
MASTER RESET (MRS1, MRS2)
a LOW pulse to MRS1 and MRS2 simultaneously. Afterwards, the FIFO1
memory of the IDT723626/723636/723646 undergoes a complete reset by
taking its associated Master Reset (MRS1) input LOW for at least four Port A Clock
(CLKA) and four Port B Clock (CLKB) LOW-to-HIGH transitions. The FIFO2
memory undergoes a complete reset by taking its associated Master Reset
(MRS2) input LOW for at least four Port A Clock (CLKA) and four Port C Clock
(CLKC) LOW-to-HIGH transitions. The Master Reset inputs can switch asyn-
chronously to the clocks. A Master Reset initializes the associated read and write
pointers to the first location of the memory and forces the Full/Input Ready flag
(FFA/IRA, FFC/IRC) LOW, the Empty/Output Ready flag (EFA/ORA, EFB/
ORB) LOW, the Almost-Empty flag (AEA, AEB) LOW, and the Almost-Full flag
(AFA, AFC) HIGH. A Master Reset also forces the associated Mailbox Flag
(MBF1, MBF2) of the parallel mailbox register HIGH. After a Master Reset, the
FIFO’s Full/Input Ready flag is set HIGH after two Write clock cycles. Then the
FIFO is ready to be written to.
latches the value of the Big-Endian (BE) input for determining the order by which
bytes are transferred through ports B and C. It also latches the values of the Flag
Select (FS0, FS1) and Serial Programming Mode (SPM) inputs for choosing
the Almost-Full and Almost-Empty offset programming mode.
offset registers of FIFO2 (X2, Y2). A LOW-to-HIGH transition on the FIFO2 Master
Reset input (MRS2) latches the value of the Big-Endian (BE) input for Ports B and
C and also latches the values of the Flag Select (FS0, FS1) and Serial Programming
Mode (SPM) inputs for choosing the Almost-Full and Almost-Empty offset program-
ming method (for details see Table 1, Flag Programming, and Almost-Empty and
Almost-Full Flag Offset Programming section). The relevant Master Reset timing
diagrams can be found in Figure 4 and 5.
IRC go HIGH). MBA and MBB are "don't care" inputs
PARTIAL RESET (PRS1, PRS2)
its associated Partial Reset (PRS1) input LOW for at least four Port A Clock
(CLKA) and four Port B Clock (CLKB) LOW-to-HIGH transitions. The FIFO2
memory undergoes a limited reset by taking its associated Partial Reset (PRS2)
input LOW for at least four Port A Clock (CLKA) and four Port C Clock (CLKC)
LOW-to-HIGH transitions. The Partial Reset inputs can switch asynchronously
to the clocks. A Partial Reset initializes the internal read and write pointers and
forces the Full/Input Ready flag (FFA/IRA, FFC/IRC) LOW, the Empty/Output
Ready flag (EFA/ORA, EFB/ORB) LOW, the Almost-Empty flag (AEA, AEB)
LOW, and the Almost-Full flag (AFA, AFC) HIGH. A Partial Reset also forces
the Mailbox Flag (MBF1, MBF2) of the parallel mailbox register HIGH. After a
Partial Reset, the FIFO’s Full/Input Ready flag is set HIGH after two Write clock
cycles.
mode (FWFT or IDT Standard mode) are currently selected at the time a Partial
Reset is initiated, those settings will remain unchanged upon completion of the
IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2
unused inputs) must not be left open, rather they must be either HIGH or LOW.
After power up, a Master Reset operation must be performed by providing
A LOW-to-HIGH transition on a FlFO1 Master Reset (MRS1, MRS2) input
A LOW-to-HIGH transition on the FIFO2 Master Reset (MRS2) clears the flag
Note that MBC must be HIGH during Master Reset (until FFA/IRA and FFC/
Whatever flag offsets, programming method (parallel or serial), and timing
The FIFO1 memory of these devices undergoes a limited reset by taking
1
during Master Reset.
10
reset operation. A Partial Reset may be useful in the case where reprogramming
a FIFO following a Master Reset would be inconvenient. See Figure 6 and 7
for Partial Reset timing diagrams.
BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/FWFT)
⎯ ⎯ ⎯ ⎯ ⎯ ENDIAN SELECTION
function is active, permitting a choice of Big- or Little-Endian byte arrange-
ment for data written to Port C or read from Port B. This selection determines
the order by which bytes (or words) of data are transferred through those
ports. For the following illustrations, note that both ports B and C are configured
to have a byte (or a word) bus size.
go from LOW to HIGH will select a Big-Endian arrangement. When data is
moving in the direction from Port A to Port B, the most significant byte (word) of
the long word written to Port A will be read from Port B first; the least significant
byte (word) of the long word written to Port A will be read from Port B last. When
data is moving in the direction from Port C to Port A, the byte (word) written to
Port C first will be read from Port A as the most significant byte (word) of the long
word; the byte (word) written to Port C last will be read from Port A as the least
significant byte (word) of the long word.
go from LOW to HIGH will select a Little-Endian arrangement. When data is
moving in the direction from Port A to Port B, the least significant byte (word) of
the long word written to Port A will be read from Port B first; the most significant
byte (word) of the long word written to Port A will be read from Port B last. When
data is moving in the direction from Port C to Port A, the byte (word) written to
Port C first will be read from Port A as the least significant byte (word) of the long
word; the byte (word) written to Port C last will be read from Port A as the most
significant byte (word) of the long word. Refer to Figures 2 and 3 for illustrations
of the BE function. See Figure 4 (FIFO1 Master Reset) and 5 (FIFO2 Master
Reset) for Endian Select timing diagrams.
⎯ ⎯ ⎯ ⎯ ⎯ TIMING MODE SELECTION
choice between two possible timing modes: IDT Standard mode or First
Word Fall Through (FWFT) mode. Once the Master Reset (MRS1, MRS2)
input is HIGH, a HIGH on the BE/FWFT input during the next LOW-to-HIGH
transition of CLKA (for FIFO1) and CLKC (for FIFO2) will select IDT Standard
mode. This mode uses the Empty Flag function (EFA, EFB) to indicate whether
or not there are any words present in the FIFO memory. It uses the Full Flag
function (FFA, FFC) to indicate whether or not the FIFO memory has any free
space for writing. In IDT Standard mode, every word read from the FIFO,
including the first, must be requested using a formal read operation.
FWFT input during the next LOW-to-HIGH transition of CLKA (for FIFO1) and
CLKC (for FIFO2) will select FWFT mode. This mode uses the Output Ready
function (ORA, ORB) to indicate whether or not there is valid data at the data
outputs (A0-A35 or B0-B17). It also uses the Input Ready function (IRA, IRC)
to indicate whether or not the FIFO memory has any free space for writing. In
the FWFT mode, the first word written to an empty FIFO goes directly to the data
This is a dual purpose pin. At the time of Master Reset, the BE select
A HIGH on the BE/FWFT input when the Master Reset (MRS1, MRS2) inputs
A LOW on the BE/FWFT input when the Master Reset (MRS1, MRS2) inputs
After Master Reset, the FWFT select function is available, permitting a
Once the Master Reset (MRS1, MRS2) input is HIGH, a LOW on the BE/
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