IDT723626L15PF IDT, Integrated Device Technology Inc, IDT723626L15PF Datasheet - Page 31

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IDT723626L15PF

Manufacturer Part Number
IDT723626L15PF
Description
IC FIFO SYNC 256X36X2 128QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
7200r
Datasheet

Specifications of IDT723626L15PF

Function
Synchronous
Memory Size
18.4K (256 x 36 x 2)
Data Rate
67MHz
Access Time
15ns
Voltage - Supply
4.5 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-TQFP, 128-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
723626L15PF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT723626L15PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT723626L15PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTES:
1. t
2. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. If Port B size is word or byte, AEB is set LOW by the last word or byte read from FIFO1, respectively.
NOTES:
1. t
2. If Port C size is word or byte, FFC is set LOW by the last word or byte write of the long word, respectively (the word-size case is shown).
IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2
C0-C17
CLKA
RENB
A0-A35
CLKB
ENA
AEB
and rising CLKB edge is less than t
CLKA
W/RA
CLKC
SKEW2
and rising CLKC edge is less than t
SKEW1
MBA
CSA
ENA
EFA
MBC
ENC
FFC
is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge
is the minimum time between a rising CLKA edge and a rising CLKC edge for FFC to transition HIGH in the next CLKC cycle. If the time between the rising CLKA edge
LOW
FIFO2 Full
LOW
LOW
HIGH
Previous Word in FIFO2 Output Register
t
CLKH
t
ENS2
t
Figure 23. FFC
CLK
t
Figure 24. Timing for AEB
ENS2
t
CLKL
SKEW2
SKEW1
FFC
FFC
FFC
FFC Flag Timing and First Available Write when FIFO2 is Full (IDT Standard Mode)
, then AEB may transition HIGH one CLKB cycle later than shown.
, then FFC may transition HIGH one CLKC cycle later than shown.
t
t
SKEW2
ENH
t
SKEW1
X1 Word in FIFO1
t
t
A
ENH
(1)
AEB
AEB
AEB
AEB when FIFO1 is Almost-Empty (IDT Standard and FWFT Modes)
(1)
1
1
t
CLKH
t
CLK
t
CLKL
31
2
2
t
WFF
t
PAE
Next Word From FIFO2
t
t
ENS2
ENS2
t
DS
Write
COMMERCIAL TEMPERATURE RANGE
(X1+1) Words in FIFO1
t
DH
t
ENS2
t
DS
t
t
WFF
ENH
t
t
DH
PAE
t
t
ENH
ENH
3271 drw24
3271 drw25

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