IDT723626L15PF IDT, Integrated Device Technology Inc, IDT723626L15PF Datasheet - Page 15

• Manufacturer Part Number: IDT723626L15PF
• Description: IC FIFO SYNC 256X36X2 128QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT723626L15PF

• Function: Synchronous
• Memory Size: 18.4K (256 x 36 x 2)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 723626L15PF

data appear on A18-A35. (In this case, A0-A17 are indeterminate.) For a 9-
bit bus size, 9 bits of mailbox data appear on A18-A26. (In this case, A0-A17
and A27-A35 are indeterminate.)
when new data is written to the register. The Endian Select feature has no effect
on mailbox data.
IRC go HIGH. MBA and MBB are don't care inputs during Master Reset. For
mail registers and mail register flag timing diagrams, see Figure 28 and 29.
BUS SIZING
for data read from FIFO1. Port C may be configured in either an 18-bit word
or a 9-bit byte format for data written to FIFO2. The bus size can be selected
independently for Ports B and C. The level applied to the Port B Size Select
(SIZEB) input determines the Port B bus size and the level applied to the
Port C Size Select (SIZEC) input determines the Port C bus size. These
levels should be static throughout FIFO operation. Both bus size selections
are implemented at the completion of Master Reset, by the time the Full/
Input Ready flag is set HIGH, as shown in Figures 2 and 3.
Ports B and C regardless of whether the bus size selection is byte- or word-
size. They are referred to as Big-Endian (most significant byte first) and
Little-Endian (least significant byte first). The level applied to the Big-
Endian Select (BE) input during the LOW-to-HIGH transition of MRS1 and
MRS2 selects the endian method that will be active during FIFO operation. This
selection applies to both ports B and C. The endian method is implemented at
the completion of Master Reset, by the time the Full/Input Ready flag is set HIGH,
as shown in Figures 2 and 3 (see Endian Selection section).
on these devices. Bus-matching operations are done after data is read from the
FIFO1 RAM (Port B) and before data is written to the FIFO2 RAM (Port C).
IDT723626/723636/723646 CMOS TRIPLE BUS SyncFIFO™
WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2 and 1,024 x 36 x 2
The data in a mail register remains intact after it is read and changes only
Note that MBC must be HIGH during Master Reset (until FFA/IRA and FFC/
Port B may be configured in either an 18-bit word or a 9-bit byte format
Two different methods for sequencing data transfer are available for
Only 36-bit long word data is written to or read from the two FIFO memories
15
The Endian Select operations are not available when transferring data via
mailbox registers. Furthermore, both the word- and byte-size bus selections limit
the width of the data bus that can be used for mail register operations. In this case,
only those byte lanes belonging to the selected word- or byte-size bus can carry
mailbox data. The remaining data outputs will be indeterminate. The remaining
data inputs will be don’t care inputs. For example, when a word-size bus is
selected on Port B, then mailbox data can be transmitted only from A0-A17 to
B0-B17. When a byte-size bus is selected on Port B, then mailbox data can be
transmitted only from A0-A8 to B0-B8. Similarly, when a word-size bus is
selected on Port C, then mailbox data can be transmitted only from C0-C17 to
A18-A35. When a byte-size bus is selected on Port C, then mailbox data can
be transmitted only from C0-C8 to A18-A26. (See Figures 28 and 29).
BUS-MATCHING FIFO1 READS
Port B can have a byte or word size, only the first one or two bytes appear
on the selected portion of the FIFO1 output register, with the rest of the long
word stored in auxiliary registers. In this case, subsequent FIFO1 reads
output the rest of the long word to the FIFO1 output register in the order
shown by Figure 2.
outputs are indeterminate.
BUS-MATCHING FIFO2 WRITES
written to FIFO2 with a byte or word bus size stores the initial bytes or words
in auxiliary registers. The CLKC rising edge that writes the fourth byte or the
second word of long word to FIFO2 also stores the entire long word in the
FIFO2 memory. The bytes are arranged in the manner shown in Figure 3.
are don't care inputs.
Data is read from the FIFO1 RAM in 36-bit long word increments. Since
When reading data from FIFO1 in byte format, the unused B9-B17
Data is written to the FIFO2 RAM in 36-bit long word increments. Data
When writing data to FIFO2 in byte format, the unused C9-C17 inputs
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