IDT72T1845L4-4BB IDT, Integrated Device Technology Inc, IDT72T1845L4-4BB Datasheet - Page 36

• Manufacturer Part Number: IDT72T1845L4-4BB
• Description: IC FIFO 2048X18 2.5V 4NS 240BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T1845L4-4BB

• Function: Asynchronous, Dual Port
• Memory Size: 36.8K (2K x 18)
• Data Rate: 10MHz
• Access Time: 3.4ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 240-BGA
• Configuration: Dual
• Density: 36Kb
• Access Time (max): 3.4/8ns
• Word Size: 9/18Bit
• Organization: 2Kx18/4Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: PBGA
• Clock Freq (max): 225/100MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Supply Current: 60mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T1845L4-4BB

NOTES:
1. t
2. LD = HIGH, OE = LOW, EF = HIGH.
3. WCS = LOW.
NOTES:
1. t
2. LD = HIGH.
3. First data word latency = t
4. RCS is LOW.
Q
D
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
Q0 - Qn
D0 - Dn
WCLK
0
0
WCLK
WCS
RCLK
RCLK
rising edge of the RCLK and the rising edge of the WCLK is less than t
rising edge of WCLK and the rising edge of RCLK is less than t
WEN
SKEW1
WEN
SKEW1
RCS
REN
- D
- Q
REN
FF
EF
OE
n
n
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle pus t
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus t
t
ENS
t
t
ENS
ENS
Figure 12. Read Cycle, Output Enable, Empty Flag and First Data Word Latency (IDT Standard Mode)
t
RCSLZ
t
SKEW1
t
t
OLZ
ENH
SKEW1
t
REF
t
A
(1)
t
OE
+ 1*T
t
WCSS
t
ENH
t
SKEW1
t
RCLK
ENS
t
A
t
DS
1
D
(1)
+ t
NO WRITE
Figure 11. Write Cycle and Full Flag Timing (IDT Standard Mode)
0
REF.
NO OPERATION
t
t
DH
ENH
LAST WORD
1
2
t
WFF
SKEW1
t
DS
t
, then EF deassertion may be delayed one extra RCLK cycle.
t
OHZ
t
CLKH
t
DS
SKEW1
ENS
D
, then the FF deassertion may be delayed one extra WCLK cycle.
D
X
1
NO OPERATION
t
WFF
DATA READ
t
t
t
36
ENH
WCSH
DH
t
DH
t
CLK
2
t
CLKL
t
t
CLKH
ENS
t
REF
t
OLZ
t
SKEW1
2Kx18/4Kx9, 4Kx18/
t
CLK
(1)
t
CLKL
t
t
ENS
ENH
LAST WORD
t
A
1
NO WRITE
t
ENH
t
A
COMMERCIAL AND INDUSTRIAL
2
TEMPERATURE RANGES
NEXT DATA READ
WFF
REF
t
t
ENS
FEBRUARY 10, 2009
WFF
t
DS
). If the time between the
). If the time between the
D
0
D
X+1
t
REF
t
t
ENH
A
5909 drw15
t
DH
5909 drw16
t
WFF
D
1