IDT72T1845L4-4BB IDT, Integrated Device Technology Inc, IDT72T1845L4-4BB Datasheet - Page 4

• Manufacturer Part Number: IDT72T1845L4-4BB
• Description: IC FIFO 2048X18 2.5V 4NS 240BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T1845L4-4BB

• Function: Asynchronous, Dual Port
• Memory Size: 36.8K (2K x 18)
• Data Rate: 10MHz
• Access Time: 3.4ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 240-BGA
• Configuration: Dual
• Density: 36Kb
• Access Time (max): 3.4/8ns
• Word Size: 9/18Bit
• Organization: 2Kx18/4Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: PBGA
• Clock Freq (max): 225/100MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Supply Current: 60mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T1845L4-4BB

DESCRIPTION:
72T18105/72T18115/72T18125 are exceptionally deep, extremely high
speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write
controls and a flexible Bus-Matching x18/x9 data flow. These FIFOs offer
several key user benefits:
• Flexible x18/x9 Bus-Matching on both read and write ports
• A user selectable MARK location for retransmit
• User selectable I/O structure for HSTL or LVTTL
• Asynchronous/Synchronous translation on the read or write ports
• The first word data latency period, from the time the first word is written to an
• High density offerings up to 9 Mbit
video, telecommunications, data communications and other applications that
need to buffer large amounts of data and match busses of unequal sizes.
which can assume either a 18-bit or a 9-bit width as determined by the state of
external control pins Input Width (IW) and Output Width (OW) pin during the
Master Reset cycle.
or Asynchronous interface. During Synchronous operation the input port is
controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data
present on the Dn data inputs is written into the FIFO on every rising edge of
WCLK when WEN is asserted. During Asynchronous operation only the WR
input is used to write data into the FIFO. Data is written on a rising edge of WR,
the WEN input should be tied to its active state, (LOW).
or Asynchronous interface. During Synchronous operation the output port is
controlled by a Read Clock (RCLK) input and Read Enable (REN) input. Data
is read from the FIFO on every rising edge of RCLK when REN is asserted.
During Asynchronous operation only the RD input is used to read data from the
FIFO. Data is read on a rising edge of RD, the REN input should be tied to its
active state, LOW. When Asynchronous operation is selected on the output port
the FIFO must be configured for Standard IDT mode, also the RCS should be
tied LOW and the OE input used to provide three-state control of the outputs, Qn.
this operation is selected by the state of the RHSTL input during a master reset.
A Read Chip Select (RCS) input is also provided, the RCS input is synchronized
to the read clock, and also provides three-state control of the Qn data outputs.
When RCS is disabled, the data outputs will be high impedance. During
Asynchronous operation of the output port, RCS should be enabled, held LOW.
provided. These are outputs from the read port of the FIFO that are required
for high speed data communication, to provide tighter synchronization between
the data being transmitted from the Qn outputs and the data being received by
the input device. Data read from the read port is available on the output bus with
respect to EREN and ERCLK, this is very useful when data is being read at
high speed. The ERCLK and EREN outputs are non-functional when the Read
port is setup for Asynchronous mode.
to f
of the one clock input with respect to the other.
Standard mode and First Word Fall Through (FWFT) mode.
on the data output lines unless a specific read operation is performed. A read
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
empty FIFO to the time it can be read, is fixed and short.
MAX
Bus-Matching TeraSync FIFOs are particularly appropriate for network,
Each FIFO has a data input port (D
The input port can be selected as either a Synchronous (clocked) interface,
The output port can be selected as either a Synchronous (clocked) interface,
The output port can be selected for either 2.5V LVTTL or HSTL operation,
An Output Enable (OE) input is provided for three-state control of the outputs.
Echo Read Enable, EREN and Echo Read Clock, ERCLK outputs are
The frequencies of both the RCLK and the WCLK signals may vary from 0
In IDT Standard mode, the first word written to an empty FIFO will not appear
There are two possible timing modes of operation with these devices: IDT
The IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895/
with complete independence. There are no restrictions on the frequency
n
) and a data output port (Q
n
), both of
4
operation, which consists of activating REN and enabling a rising RCLK edge,
will shift the word from internal memory to the data output lines.
to the data output lines after three transitions of the RCLK signal. A REN does
not have to be asserted for accessing the first word. However, subsequent
words written to the FIFO do require a LOW on REN for access. The state of
the FWFT/SI input during Master Reset determines the timing mode in use.
can provide, the FWFT timing mode permits depth expansion by chaining FIFOs
in series (i.e. the data outputs of one FIFO are connected to the corresponding
data inputs of the next). No external logic is required.
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and FF
functions are selected in IDT Standard mode. The IR and OR functions are
selected in FWFT mode. HF, PAE and PAF are always available for use,
irrespective of timing mode.
memory. Programmable offsets determine the flag switching threshold and can
be loaded by two methods: parallel or serial. Eight default offset settings are also
provided, so that PAE can be set to switch at a predefined number of locations
from the empty boundary and the PAF threshold can also be set at similar
predefined values from the full boundary. The default offset values are set during
Master Reset by the state of the FSEL0, FSEL1, and LD pins.
SCLK, are used to load the offset registers via the Serial Input (SI). For parallel
programming, WEN together with LD on each rising edge of WCLK, are used
to load the offset registers via D
of RCLK can be used to read the offsets in parallel from Q
serial or parallel offset loading has been selected.
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standard mode or FWFT mode.
location of the memory. However, the timing mode, programmable flag
programming method, and default or programmed offset settings existing before
Partial Reset remain unchanged. The flags are updated according to the timing
mode and offsets in effect. PRS is useful for resetting a device in mid-operation,
when reprogramming programmable flags would be undesirable.
Empty flag) and PAF (Programmable Almost-Full flag) outputs. The timing
modes can be set to be either asynchronous or synchronous for the PAE and
PAF flags.
LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOW-
to-HIGH transition of WCLK. Similarly, the PAF is asserted LOW on the LOW-
to-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH
transition of RCLK.
updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is
asserted and updated on the rising edge of WCLK only and not RCLK. The mode
desired is configured during Master Reset by the state of the Programmable Flag
Mode (PFM) pin.
inputs, MARK and , RT (Retransmit). If the MARK input is enabled with respect
to the RCLK, the memory location being read at that point will be marked. Any
subsequent retransmit operation, RT goes LOW, will reset the read pointer to
this ‘marked’ location.
In FWFT mode, the first word written to an empty FIFO is clocked directly
For applications requiring more data storage capacity than a single FIFO
PAE and PAF can be programmed independently to switch at any point in
For serial programming, SEN together with LD on each rising edge of
During Master Reset (MRS) the following events occur: the read and write
The Partial Reset (PRS) also sets the read and write pointers to the first
It is also possible to select the timing mode of the PAE (Programmable Almost-
If asynchronous PAE/PAF configuration is selected, the PAE is asserted
If synchronous PAE/PAF configuration is selected , the PAE is asserted and
This device includes a Retransmit from Mark feature that utilizes two control
These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready),
2Kx18/4Kx9, 4Kx18/
n
. REN together with LD on each rising edge
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 10, 2009
n
regardless of whether