IDT72T1845L4-4BB IDT, Integrated Device Technology Inc, IDT72T1845L4-4BB Datasheet - Page 49

• Manufacturer Part Number: IDT72T1845L4-4BB
• Description: IC FIFO 2048X18 2.5V 4NS 240BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T1845L4-4BB

• Function: Asynchronous, Dual Port
• Memory Size: 36.8K (2K x 18)
• Data Rate: 10MHz
• Access Time: 3.4ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 240-BGA
• Configuration: Dual
• Density: 36Kb
• Access Time (max): 3.4/8ns
• Word Size: 9/18Bit
• Organization: 2Kx18/4Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: PBGA
• Clock Freq (max): 225/100MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Supply Current: 60mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T1845L4-4BB

NOTE:
1. The O/P Register is the internal output register. Its contents are available on the Qn output bus only when RCS and OE are both active, LOW, that is the bus is not in High-
2. OE is LOW.
Cycle:
a&b. At this point the FIFO is empty, OR is HIGH.
c.
d .
e.
f.
g .
h .
i .
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
D0 - Dn
ERCLK
Impedance state.
WCLK
EREN
RCLK
WEN
REN
RCS
Reg.
O/P
OR
Qn
RCS and REN are both disabled, the output bus is High-Impedance.
Word Wn+1 falls through to the output register, OR goes active, LOW.
RCS is HIGH, therefore the Qn outputs are High-Impedance. EREN goes LOW to indicate that a new word has been placed on the output register.
EREN goes HIGH, no new word has been placed on the output register on this cycle.
No Operation.
RCS is LOW on this cycle, therefore the Qn outputs go to Low-Impedance and the contents of the output register (Wn+1) are made available.
NOTE: In FWFT mode is important to take RCS active LOW at least one cycle ahead of REN, this ensures the word (Wn+1) currently in the output register is made
available for at least one cycle.
REN goes active LOW, this reads out the second word, Wn+2.
EREN goes active LOW to indicate a new word has been placed into the output register.
Word Wn+3 is read out, EREN remains active, LOW indicating a new word has been read out.
NOTE: Wn+3 is the last word in the FIFO.
This is the next enabled read after the last word, Wn+3 has been read out. OR flag goes HIGH and EREN goes HIGH to indicate that there is no new word available.
HIGH-Z
t
ENS
t
DS
W
t
ERCLK
n+1
W
t
DH
n
t
Last Word
SKEW1
t
DS
Figure 29. Echo RCLK and Echo REN
a
W
n+2
t
DH
1
b
t
DS
W
n+3
t
DH
2
t
ENH
c
t
t
t
REF
CLKEN
A
d
49
REN
REN
REN Operation (FWFT Mode Only)
REN
t
CLKEN
e
W
n+1
2Kx18/4Kx9, 4Kx18/
t
ENS
f
t
RCSLZ
t
ENS
W
n+1
g
t
t
t
A
A
CLKEN
COMMERCIAL AND INDUSTRIAL
W
W
n+2
n+2
h
TEMPERATURE RANGES
t
t
A
A
FEBRUARY 10, 2009
W
W
i
n+3
t
n+3
ENH
t
t
REF
CLKEN
5909 drw33