LM3S6110 Luminary Micro, Inc, LM3S6110 Datasheet - Page 298

• Manufacturer Part Number: LM3S6110
• Description: Lm3s6110 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Synchronous Serial Interface (SSI)
SSI Clock Prescale (SSICPSR)
SSI0 base: 0x4000.8000
Offset 0x010
Type R/W, reset 0x0000.0000
298
Bit/Field
31:8
7:0
RO
RO
31
15
0
0
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010
SSICPSR is the clock prescale register and specifies the division factor by which the system clock
must be internally divided before further use.
The value programmed into this register must be an even number between 2 and 254. The
least-significant bit of the programmed number is hard-coded to zero. If an odd number is written
to this register, data read back from this register has the least-significant bit as zero.
RO
RO
30
14
0
0
CPSDVSR
reserved
RO
RO
29
13
0
0
Name
RO
RO
28
12
0
0
reserved
RO
RO
27
11
0
0
Type
R/W
RO
RO
RO
26
10
0
0
Reset
0x00
0x00
RO
RO
25
0
9
0
Preliminary
RO
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Clock Prescale Divisor
This value must be an even number from 2 to 254, depending on the
frequency of SSIClk. The LSB always returns 0 on reads.
reserved
R/W
RO
23
0
7
0
R/W
RO
22
0
6
0
R/W
RO
21
0
5
0
R/W
RO
20
0
4
0
CPSDVSR
R/W
RO
19
0
3
0
R/W
RO
18
0
2
0
July 25, 2008
R/W
RO
17
0
1
0
R/W
RO
16
0
0
0