LM3S6110 Luminary Micro, Inc, LM3S6110 Datasheet - Page 8

• Manufacturer Part Number: LM3S6110
• Description: Lm3s6110 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Table of Contents
List of Figures
Figure 1-1.
Figure 2-1.
Figure 2-2.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 6-1.
Figure 6-2.
Figure 6-3.
Figure 7-1.
Figure 8-1.
Figure 8-2.
Figure 8-3.
Figure 9-1.
Figure 9-2.
Figure 9-3.
Figure 9-4.
Figure 10-1.
Figure 11-1.
Figure 11-2.
Figure 11-3.
Figure 12-1.
Figure 12-2.
Figure 12-3.
Figure 12-4.
Figure 12-5.
Figure 12-6.
Figure 12-7.
Figure 12-8.
Figure 12-9.
Figure 12-10. MICROWIRE Frame Format (Single Frame) .................................................................... 287
Figure 12-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 288
Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 288
Figure 13-1.
Figure 13-2.
Figure 13-3.
Figure 14-1.
Figure 14-2.
Figure 14-3.
Figure 15-1.
Figure 15-2.
Figure 15-3.
Figure 15-4.
Figure 15-5.
8
Stellaris
CPU Block Diagram ......................................................................................................... 35
TPIU Block Diagram ........................................................................................................ 36
JTAG Module Block Diagram ............................................................................................ 46
Test Access Port State Machine ....................................................................................... 49
IDCODE Register Format ................................................................................................. 54
BYPASS Register Format ................................................................................................ 55
Boundary Scan Register Format ....................................................................................... 55
External Circuitry to Extend Reset .................................................................................... 57
Power Architecture .......................................................................................................... 60
Main Clock Tree .............................................................................................................. 62
Flash Block Diagram ...................................................................................................... 114
GPIO Port Block Diagram ............................................................................................... 139
GPIODATA Write Example ............................................................................................. 140
GPIODATA Read Example ............................................................................................. 140
GPTM Module Block Diagram ........................................................................................ 180
16-Bit Input Edge Count Mode Example .......................................................................... 184
16-Bit Input Edge Time Mode Example ........................................................................... 185
16-Bit PWM Mode Example ............................................................................................ 186
WDT Module Block Diagram .......................................................................................... 215
UART Module Block Diagram ......................................................................................... 239
UART Character Frame ................................................................................................. 240
IrDA Data Modulation ..................................................................................................... 242
SSI Module Block Diagram ............................................................................................. 279
TI Synchronous Serial Frame Format (Single Transfer) .................................................... 282
TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 282
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 283
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 283
Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 284
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 285
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 285
Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 286
Ethernet Controller Block Diagram .................................................................................. 317
Ethernet Controller ......................................................................................................... 317
Ethernet Frame ............................................................................................................. 319
Analog Comparator Module Block Diagram ..................................................................... 361
Structure of Comparator Unit .......................................................................................... 362
Comparator Internal Reference Structure ........................................................................ 363
PWM Unit Diagram ........................................................................................................ 373
PWM Module Block Diagram .......................................................................................... 374
PWM Count-Down Mode ................................................................................................ 375
PWM Count-Up/Down Mode .......................................................................................... 375
PWM Generation Example In Count-Up/Down Mode ....................................................... 376
®
6000 Series High-Level Block Diagram ............................................................... 28
Preliminary
July 25, 2008