LM3S8933 Luminary Micro, Inc, LM3S8933 Datasheet - Page 103

• Manufacturer Part Number: LM3S8933
• Description: Lm3s8933 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Deep Sleep Mode Clock Gating Control Register 0 (DCGC0)
Base 0x400F.E000
Offset 0x120
Type R/W, reset 0x00000040
July 25, 2008
Bit/Field
31:25
23:17
15:10
24
16
RO
RO
31
15
0
0
Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0),
offset 0x120
This register controls the clock gating logic. Each bit controls a clock enable for a given interface,
function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and
disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
The reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are
disabled. It is the responsibility of software to enable the ports necessary for the application. Note
that these registers may contain more bits than there are interfaces, functions, or units to control.
This is to assure reasonable code compatibility with other family and future parts. RCGC0 is the
clock configuration register for running operation, SCGC0 for Sleep operation, and DCGC0 for
Deep-Sleep operation. Setting the ACG bit in the Run-Mode Clock Configuration (RCC) register
specifies that the system uses sleep modes.
RO
RO
30
14
0
0
reserved
reserved
reserved
RO
RO
29
13
0
0
Name
CAN0
ADC
reserved
reserved
RO
RO
28
12
0
0
RO
RO
27
11
0
0
Type
R/W
R/W
RO
RO
RO
RO
RO
26
10
0
0
Reset
R/W
RO
MAXADCSPD
25
0
9
0
0
0
0
0
0
Preliminary
CAN0
R/W
R/W
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
CAN0 Clock Gating Control
This bit controls the clock gating for CAN unit 0. If set, the unit receives
a clock and functions. Otherwise, the unit is unclocked and disabled.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ADC0 Clock Gating Control
This bit controls the clock gating for SAR ADC module 0. If set, the unit
receives a clock and functions. Otherwise, the unit is unclocked and
disabled. If the unit is unclocked, a read or write to the unit generates
a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
reserved
RO
RO
23
0
7
0
R/W
HIB
RO
22
0
6
0
RO
RO
21
0
5
0
reserved
reserved
RO
RO
20
0
4
0
LM3S8933 Microcontroller
WDT
R/W
RO
19
0
3
0
RO
RO
18
0
2
0
reserved
RO
RO
17
0
1
0
ADC
R/W
RO
16
0
0
0
103