LM3S8933 Luminary Micro, Inc, LM3S8933 Datasheet - Page 462

• Manufacturer Part Number: LM3S8933
• Description: Lm3s8933 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Ethernet Controller
17.2.3.3 Ethernet Transmission Options
17.2.3.4 Ethernet Reception Options
17.2.3.5 Packet Timestamps
462
The Ethernet Controller can automatically generate and insert the Frame Check Sequence (FCS)
at the end of the transmit frame. This is controlled by the CRC bit in the MACTCTL register. For test
purposes, in order to generate a frame with an invalid CRC, this feature can be disabled.
The IEEE 802.3 specification requires that the Ethernet frame payload section be a minimum of 46
bytes. The Ethernet Controller can be configured to automatically pad the data section if the payload
data section loaded into the FIFO is less than the minimum 46 bytes. This feature is controlled by
the PADEN bit in the MACTCTL register.
At the MAC layer, the transmitter can be configured for both full-duplex and half-duplex operation
by using the DUPLEX bit in the MACTCTL register.
Using the BADCRC bit in the MACRCTL register, the Ethernet Controller can be configured to reject
incoming Ethernet frames with an invalid FCS field.
The Ethernet receiver can also be configured for Promiscuous and Multicast modes using the PRMS
and AMUL fields in the MACRCTL register. If these modes are not enabled, only Ethernet frames
with a broadcast address, or frames matching the MAC address programmed into the MACIA0 and
MACIA1 register is placed into the RX FIFO.
Using the TSEN bit in the MACTS register, the MAC transmit and receive interrupts can be used to
trigger edge capture events on General-Purpose Timer 3. The transmit interrupt is routed to the
CCP (even) input of General-Purpose Timer 3, while the receive interrupt is routed to the CCP (odd)
input of General-Purpose Timer 3. This timer can then be configured in 16-bit edge capture mode
FIFO Word Read/Write
Sequence
3rd
4th
5th to nth
last
Word Bit Fields
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
Preliminary
TX FIFO (Write)
FCS 1 (if the CRC bit in
MACCTL is 0)
FCS 2 (if the CRC bit in
MACCTL is 0)
FCS 3 (if the CRC bit in
MACCTL is 0)
FCS 4 (if the CRC bit in
MACCTL is 0)
Len/Type MSB
Len/Type LSB
data oct n+1
data oct n+2
data oct n+3
data oct n
SA oct 1
SA oct 2
SA oct 3
SA oct 4
SA oct 5
SA oct 6
RX FIFO (Read)
FCS 1
FCS 2
FCS 3
FCS 4
July 25, 2008