LM3S300 Luminary Micro, Inc, LM3S300 Datasheet - Page 236

• Manufacturer Part Number: LM3S300
• Description: Lm3s300 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Universal Asynchronous Receivers/Transmitters (UARTs)
UART Interrupt FIFO Level Select (UARTIFLS)
UART0 base: 0x4000.C000
UART1 base: 0x4000.D000
Offset 0x034
Type R/W, reset 0x0000.0012
236
Bit/Field
31:6
5:3
RO
RO
31
15
0
0
RO
RO
Register 8: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034
The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define
the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered.
The interrupts are generated based on a transition through a level rather than being based on the
level. That is, the interrupts are generated when the fill level progresses through the trigger level.
For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the
module is receiving the 9th character.
Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt
at the half-way mark.
30
14
0
0
RXIFLSEL
RO
RO
29
13
reserved
0
0
Name
RO
RO
28
12
0
0
RO
RO
27
11
0
0
reserved
Type
R/W
RO
RO
RO
26
10
0
0
RO
RO
Reset
25
0x00
0
9
0
0x2
Preliminary
RO
RO
24
0
8
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
UART Receive Interrupt FIFO Level Select
The trigger points for the receive interrupt are as follows:
0x5-0x7
Value
0x0
0x1
0x2
0x3
0x4
RO
RO
23
0
7
0
Description
RX FIFO ≥ 1/8 full
RX FIFO ≥ ¼ full
RX FIFO ≥ ½ full (default)
RX FIFO ≥ ¾ full
RX FIFO ≥ 7/8 full
Reserved
RO
RO
22
0
6
0
R/W
RO
21
0
5
0
RXIFLSEL
R/W
RO
20
0
4
1
R/W
RO
19
0
3
0
R/W
RO
18
0
2
0
TXIFLSEL
R/W
RO
17
0
1
1
June 04, 2008
R/W
RO
16
0
0
0