LM3S3749 Luminary Micro, Inc, LM3S3749 Datasheet - Page 484

• Manufacturer Part Number: LM3S3749
• Description: Lm3s3749 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Inter-Integrated Circuit (I
Write-Only Control Register
I2C Master Control/Status (I2CMCS)
I2C Master 0 base: 0x4002.0000
I2C Master 1 base: 0x4002.1000
Offset 0x004
Type WO, reset 0x0000.0000
484
Bit/Field
Bit/Field
31:4
WO
WO
3
2
1
0
3
2
31
15
0
0
WO
WO
30
14
0
0
WO
WO
ADRACK
29
13
DATACK
reserved
ERROR
0
0
Name
BUSY
Name
STOP
ACK
2
C) Interface
WO
WO
28
12
0
0
WO
WO
27
11
0
0
Type
Type
WO
WO
WO
RO
RO
RO
RO
WO
WO
26
10
0
0
reserved
WO
WO
Reset
Reset
25
0x00
0
9
0
0
0
0
0
0
0
Preliminary
WO
WO
24
0
8
0
reserved
Description
Acknowledge Data
This bit specifies the result of the last data operation. If set, the
transmitted data was not acknowledged; otherwise, the data was
acknowledged.
Acknowledge Address
This bit specifies the result of the last address operation. If set, the
transmitted address was not acknowledged; otherwise, the address was
acknowledged.
Error
This bit specifies the result of the last bus operation. If set, an error
occurred on the last operation; otherwise, no error was detected. The
error can be from the slave address not being acknowledged, the
transmit data not being acknowledged, or because the controller lost
arbitration.
I
This bit specifies the state of the controller. If set, the controller is busy;
otherwise, the controller is idle. When the BUSY bit is set, the other status
bits are not valid.
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Data Acknowledge Enable
When set, causes received data byte to be acknowledged automatically
by the master. See field decoding in Table 16-3 on page 485.
Generate STOP
When set, causes the generation of the STOP condition. See field
decoding in Table 16-3 on page 485.
2
C Busy
WO
WO
23
0
7
0
WO
WO
22
0
6
0
WO
WO
21
0
5
0
WO
WO
20
0
4
0
ACK
WO
WO
19
0
3
0
STOP
WO
WO
18
0
2
0
START
WO
WO
17
0
1
0
June 02, 2008
RUN
WO
WO
16
0
0
0