LM3S3749 Luminary Micro, Inc, LM3S3749 Datasheet - Page 550

• Manufacturer Part Number: LM3S3749
• Description: Lm3s3749 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Univeral Serial Bus (USB) Controller
550
Bit/Field
2
1
0
STALLED
RXRDY
TXRDY
Name
R/W0C
R/W1S
Type
RO
Reset
0
0
0
Preliminary
Description
Endpoint Stalled
This bit is set when a STALL handshake is transmitted. The CPU should
clear this bit by writing a 0. This bit can only be cleared. Setting this bit
does nothing.
Transmit Packet Ready
The CPU writes a 1 to this bit after loading a data packet into the FIFO.
It is cleared automatically when the data packet has been transmitted.
An interrupt is also generated at this point.
Receive Packet Ready
This bit is set when a data packet has been received. An interrupt is
generated when this bit is set. The CPU clears this bit by setting the
RXRDYC bit.
June 02, 2008