MT9196 Mitel Semiconductor, MT9196 Datasheet - Page 12

• Manufacturer Part Number: MT9196
• Description: Integrated Digital Phone Circuit (IDPC)
• Manufacturer: Mitel Semiconductor

MT9196
beginning with Channel 0 after the frame pulse, as
shown in Figure 7 (ST-BUS channel assignments).
The first two (D & C) Channels are enabled for use
by the DEN and CEN bits respectively, (FDI Control
Register, address 10h). ISDN basic rate service
(2B+D) defines a 16kb/s signalling (D) Channel.
IDPC supports transparent access to this signalling
channel. ST-BUS basic rate transmission devices,
which may not employ a microport, provide access to
their internal control/status registers through the ST-
BUS Control (C) Channel. IDPC supports microport
access to this C-Channel.
DEN - D-Channel
In ST-BUS mode access to the D-Channel (transmit
and receive) data is provided through an 8-bit read/
write register (address 15h)
accumulated in, or transmitted from this register at
the rate of 2 bits/frame for 16 kb/s operation (1 bit/
frame for 8 kb/s operation). Since the ST-BUS is
asynchronous, with respect to the microport, valid
access to this register is controlled through the use
of an interrupt (IRQ) output. D-Channel access is
enabled via the (DEn) bit.
DEn:
When 1, ST-BUS D-channel data (1 or 2 bits/frame
depending on the state of the D8 bit) is shifted into/
out of the D-channel (READ/WRITE) register.
When 0, the receive D-channel data (READ) is still
shifted into the proper register while the DSTo D-
channel timeslot and IRQ outputs are tri-stated
(default).
D8:
When 1, D-Channel data is shifted at the rate of 1 bit/
frame (8 kb/s).
When 0, D-Channel data is shifted at the rate of 2
bits/frame (16 kb/s default).
16 kb/s D-Channel operation is the default mode
which allows the microprocessor access to a full byte
of D-Channel information every fourth ST-BUS
frame. By arbitrarily assigning ST-BUS frame n as
the
microprocessor D-Channel read and write operations
are performed, then:
(a) A microport read of address 15 hex will result in a
byte of data being extracted which is composed of
four di-bits (designated by roman numerals I,II,III,IV).
7-138
reference
frame,
during
D-Channel data is
which
the
These di-bits are composed of the two D-Channel
bits received during each of frames n, n-1, n-2 and n-
3. Referring to Fig. 8a: di-bit I is mapped from frame
n-3, di-bit II is mapped from frame n-2, di-bit III is
mapped from frame n-1 and di-bit IV is mapped from
frame n.
The D-Channel read register is not preset to any
particular value on power-up (PWRST) or software
reset (RST).
(b) A microport write to Address 15hex will result in a
byte of data being loaded which is composed of four
di-bits (designated by roman numerals I, II, III, IV).
These di-bits are destined for the two D-Channel bits
transmitted during each of frames n+1, n+2, n+3,
n+4. Referring to Fig.8a: di-bit I is mapped to frame
n+1, di-bit II is mapped to frame n+2, di bit III is
mapped to frame n+3 and di bit IV is mapped to
frame n+4.
If no new data is written to address 15hex , the
current
continuously re-transmitted.
register is preset to all ones on power-up (PWRST)
or software reset (RST).
An interrupt output is provided (IRQ) to synchronize
microprocessor access to the D-Channel register
during valid ST-BUS periods only. IRQ will occur
every fourth (eighth in 8 kb/s mode) ST-BUS frame
at the beginning of the third (second in 8 kb/s mode)
ST-BUS bit cell period. The interrupt will be removed
following a microprocessor Read or Write of Address
15 hex or upon encountering the following frames’s
FP input, whichever occurs first.
Channel data integrity, microport read/write access
to Address 15 hex must occur before the following
frame pulse. See Figure 8b for timing.
8 kb/s operation expands the interrupt to every eight
frames and processes data one-bit-per-frame.
Channel register data is mapped according to Figure
8c.
CEn - C-Channel
Channel 1 conveys the control/status information for
the layer 1 transceiver. C-Channel data is transferred
MSB first on the ST-BUS by IDPC. The full 64 kb/s
bandwidth is available and is assigned according to
which transceiver is being used. Consult the data
sheet for the selected transceiver for its C-Channel
bit definitions and order of bit transfer.
When CEN is high, data written to the C-Channel
register
D-channel
(address
Preliminary Information
14h)
register
is
The D-Channel write
contents
transmitted,
To ensure D-
will
most
be
D-