MT9196 Mitel Semiconductor, MT9196 Datasheet - Page 2

• Manufacturer Part Number: MT9196
• Description: Integrated Digital Phone Circuit (IDPC)
• Manufacturer: Mitel Semiconductor

MT9196
7-128
Pin Description
Pin #
10
11
12
13
14
15
1
2
3
4
5
6
7
8
9
PWRST
DATA1
DATA2
VSSD
SCLK
PWRST Power-up Reset (Input). CMOS compatible input with Schmitt Trigger (active low).
CS
DATA1
DATA2
Name
SCLK
IC
V
V
V
D
WD
IRQ
M+
CS
D
M-
IC
Bias
SSD
Ref
out
in
10
12 13 14 15 16 17 18
11
5
4
6
7
8
9
28 PIN PLCC
3 2
Inverting Microphone (Input). Inverting input to microphone amplifier from the handset
microphone.
Non-Inverting Microphone (Input). Non-inverting input to microphone amplifier from the
handset microphone.
Bias Voltage (Output). (V
Connect 0.1 µF capacitor to V
Reference voltage for codec (Output). Nominally [(V
Connect 0.1 µF capacitor to V
Internal Connection. Tie externally to V
Digital Ground. Nominally 0 volts.
Chip Select (Input). This input signal is used to select the device for microport data
transfers. Active low. TTL level compatible.
Serial Port Synchronous Clock (Input). Data clock for microport. TTL level compatible.
Bidirectional Serial Data. Port for microprocessor serial data transfer. In Motorola/National
mode of operation, this pin becomes the data transmit pin only and data receive is
performed on the DATA2 pin. TTL level compatible input levels.
Serial Data Receive. In Motorola/National mode of operation, this pin is used for data
receive to the IDPC. In Intel mode, serial data transmit and receive are performed on the
DATA1 pin and DATA2 is disconnected. Input level TTL compatible.
Watchdog (Output). Watchdog timer output. Active high.
Interrupt Request (Open Drain Output). Low true interrupt output to microcontroller.
Data Output. A tri-state digital output for 8 bit wide channel data being sent to the Layer 1
device. Data is shifted out via this pin concurrent with the rising edge of BCL during the
timeslot defined by STB, or according to standard ST-BUS timing.
Data Input. A digital input for 8 bit wide channel data received from the Layer 1 device.
Data is sampled on the falling edge of BCL during the timeslot defined by STB, or according
to standard ST-BUS timing. Input level is CMOS compatible.
1
28
27
19
25
24
23
22
21
20
26
AUXout
VSS SPKR
SPKR+
SPKR-
HSPKR+
HSPKR-
VDD
Figure 2 - Pin Connections
DD
/2) volts is available at this pin for biasing external amplifiers.
SSA
SSA
.
.
Description
SS
PWRST
for normal operation.
DATA1
DATA2
VSSD
VBias
SCLK
Dout
IRQ
WD
M+
CS
M-
IC
28 PIN SOIC/PDIP
10
11
12
13
14
1
2
3
4
5
6
7
8
9
DD
/2)-1.5] volts. Used internally.
Preliminary Information
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VSSA
MIC+
AUXin
AUXout
VSS SPKR
SPKR+
SPKR-
HSPKR+
HSPKR-
VDD
XSTAL2
CLOCKin
STB/F0i
Din