MT9196 Mitel Semiconductor, MT9196 Datasheet - Page 16

• Manufacturer Part Number: MT9196
• Description: Integrated Digital Phone Circuit (IDPC)
• Manufacturer: Mitel Semiconductor

MT9196
Sidetone
A voice sidetone path provides proportional transmit
signal summing into the receive handset transducer
driver. Details are provided in the Filter/CODEC
section.
Watchdog
To maintain program integrity an on-chip watchdog
timer
microcontroller reset pin. The watchdog output WD
goes high while the IDPC is held in reset via PWRST.
Release of PWRST will cause WD to return low
immediately and will also start the watchdog timer.
The watchdog timer is clocked on the falling edge of
STB/F0i and requires only this input, along with V
for operation.
disappears the watchdog will stop clocking. This will
not harm processor operation but there is no longer
any protection provided.
If the watchdog reset word is written to the watchdog
register (address 11h) after PWRST is released, but
before the timeout period (T=512 mSec) expires, a
reset of the timer results and WD will remain low.
Thereafter, if the reset word is loaded correctly at
intervals less than 'T' then WD will continue low. The
first break from this routine, in which the watchdog
register is not written to within the correct interval or
it is written to with incorrect data, will result in a high
going WD output after the current interval 'T' expires.
WD will then toggle at this rate until the watchdog
register is again written to correctly.
5-BIT WATCHDOG RESET WORD
x=don’t care
Power-up/down & PWRST/Software Reset
While the IDPC is held in PWRST no device control
or functionality is possible. While in software reset
(RST=1, address 0Fh) only the microport and
watchdog are functional. Software reset can only be
removed by writing RST logic low or by the PWRST
pin.
After Power-up reset (PWRST) or software reset
(RST) all control bits assume their default states;
gains and all sections of IDPC, except the microport
and watchdog, into powered down states. This is the
low power, stand-by condition. This includes:
7-142
-Law functionality, usually 0 dB programmable
B7
X
is
B6
X
provided
B5
X
Note that in SSI mode, if STB
B4
0
for
B3
1
connection
B2
0
B1
1
to
B0
0
DD
the
,
The receive output drive transducers. All
The transmit and receive filters and CODEC. All
The VRef and VBias circuits. Reference and
The FDI and oscillator circuits. After PWRST,
To power up the FDI and oscillator circuits the
To attain complete power-down from a normal
transducer output drivers are powered down
forcing the output signals into tri-state. Output
drivers (handset, handsfree-speaker, AUXout)
are powered up/down individually as required
by the state of the programmed bits in the
Receive Path Control Register (address 13h)
clocks for this circuit block are disabled. The
complete section is automatically powered up
as required by the programmed bits in the
Transmit and Receive Path Control registers
(addresses 12h and 13h). Whenever all path
control selections are off this section is
powered down. The CODEC and transmit/
receive
individually.
Bias voltage drivers are tri-stated during power
down causing the voltage at the pins to float.
This circuit block is automatically powered up/
down as it is required by either the Filter/
CODEC or the transducer driver circuits.
Whenever all path control selections are off this
section is powered down. If the AUXin path to
(any combination of the) output transducer
drivers is selected then the VRef/VBias circuit
is powered up but the Filter/CODEC circuit is
not.
the device assumes SSI operation with Dout tri-
stated while there is no strobe active on STB. If
a valid strobe is supplied to STB, then Dout will
be active, during the defined channel, supplying
quiet code as defined in Table 1. If the device
is switched to ST-BUS operation following
PWRST, the entire Dout stream will be tri-stated
until an active transmit channel is programmed.
As well, following PWRST, the oscillator circuit
is disabled and all timing for the IDPC
functional blocks is halted.
applied to the MCL pin is prevented from
entering further into the IDPC when the Asynch/
Synch bit is logic “1”.
PD bit of Control Register 1 (address 0Eh) must
be cleared.
operating condition, write all “0s” to the
Transmit and Receive Path Control Registers
(address 12h and 13h), set PD to logic 1 at
address 0Eh, and Asynch/Synch to logic 1 at
address 10h.
filters
Preliminary Information
cannot
be
A clock signal
powered
up